Intel® Quartus® Prime Pro Edition User Guide: Getting Started

Download
ID 683463
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3. Upgrade IP Cores and Platform Designer Systems

Upgrade all IP cores and Platform Designer systems in your project for migration to the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Pro Edition software uses standards-compliant methodology for instantiation and generation of IP cores and Platform Designer systems. Most Intel FPGA IP cores and Platform Designer systems upgrade automatically in the Upgrade IP Components dialog box.

Other Quartus software products use a proprietary Verilog configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. The Intel® Quartus® Prime Pro Edition does not support this scheme. To upgrade all IP cores and Platform Designer systems in your project, click Project > Upgrade IP Components.2

Table 22.  IP Core and Platform Designer System Differences
Other Quartus Software Products Intel® Quartus® Prime Pro Edition
IP and Platform Designer system generation use a proprietary Verilog HDL configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. This proprietary Verilog HDL configuration scheme prevents RTL entities from ambiguous instantiation errors during synthesis. However, these errors may manifest in simulation. Resolving this issue requires writing a Verilog HDL configuration to disambiguate the instantiation, delete the duplicate entity from the project, or rename one of the conflicting entities. Intel® Quartus® Prime Pro Edition IP strategy resolves these issues.

IP and Platform Designer system generation does not use proprietary Verilog HDL configurations. The compilation library scheme changes in the following ways:

  • Compiles all variants of an IP core into the same compilation library across the entire project. Intel® Quartus® Prime Pro Edition identically names IP cores with identical functionality and parameterization to avoid ambiguous entity instantiation errors. For example, the files for every Intel® Arria® 10 PCI Express* IP core variant compile into the altera_pcie_a10_hip_151 compilation library.
  • Simulation and synthesis file sets for IP cores and systems instantiate entities in the same manner.
  • The generated RTL directory structure now matches the compilation library structure.
Note: For complete information on upgrading IP cores, refer to Managing Intel® Quartus® Prime Projects.
2 For brevity, this section refers to Intel® Quartus® Prime Standard Edition, Intel Quartus Prime Lite Edition, and the Quartus II software collectively as "other Quartus software products."

Did you find the information on this page useful?

Characters remaining:

Feedback Message