Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.4.1.1. Verilog HDL Configuration Instantiation

Intel® Quartus® Prime Pro Edition synthesis requires instantiation of the Verilog HDL configuration, and not the module. In other Quartus software products, synthesis automatically finds any Verilog HDL configuration relating to a module that you instantiate. The Verilog HDL configuration then instantiates the design.

If your top-level entity is a Verilog HDL configuration, set the Verilog HDL configuration, rather than the module, as the top-level entity.

Table 24.  Verilog HDL Configuration Instantiation
Other Quartus Software Products Intel® Quartus® Prime Pro Edition
From the Example RTL, synthesis automatically finds the mid_config Verilog HDL configuration relating to the instantiated module. From the Example RTL, synthesis does not find the mid_config Verilog HDL configuration. You must instantiate the Verilog HDL configuration directly.

Example RTL:

config mid_config;
design good_lib.mid;
instance mid.sub_inst use good_lib.sub;
endconfig

module test (input a1, output b);
mid_config mid_inst ( .a1(a1), .b(b)); 
// in other Quartus products preceding line would have been: 
//mid mid_inst ( .a1(a1), .b(b));
endmodule

module mid (input a1, output b);
sub sub_inst (.a1(a1), .b(b));
endmodule

Did you find the information on this page useful?

Characters remaining:

Feedback Message