Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 3/28/2022
Public

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4.10. Simulating Platform Designer Systems

You can simulate your Platform Designer system in a supported third-party simulator to verify and debug system operation. When you Generate HDL for your system or IP component, Platform Designer can also optionally generate the corresponding simulation models, along with scripts to set up your supported simulator.

To generate the simulation model and simulator setup scripts for your Platform Designer system or component, follow these steps:

  1. In Platform Designer, click Generate > Generate HDL. The Generation dialog box appears.
  2. Under Simulation, specify Verilog or VHDL for the Create simulation model option.
  3. Turn on or off the ModelSim, VCS-MX, VCS, Riviera-Pro, or Xcelium option to generate simulator setup scripts for the simulation tool. If you turn on no simulator options, the scripts generate for all simulators.
  4. Click the Generate button. Platform Designer generates the simulation models and setup scripts for your system or IP component in the following directory:
    <top-level system name>/<system name>/<sim>/<simulator>
    Figure 57. Simulation Options in Generation Dialog Box
    Figure 58. Generated Simulation Files Location

By default, Platform Designer generates the simulation scripts for the currently loaded system and all subsystems. Alternatively, you can open a subsystem to generate a simulation script only for that subsystem.

You can use scripts to compile the required device libraries and system design files in the correct order and elaborate or load the top-level system for simulation.

Table 20.  Simulation Script VariablesThe simulation scripts provide variables that allow flexibility in your simulation environment.
Variable Description
TOP_LEVEL_NAME If the testbench Platform Designer system is not the top‑level instance in your simulation environment because you instantiate the Platform Designer testbench within your own top-level simulation file, set the TOP_LEVEL_NAME variable to the top-level hierarchy name.
QSYS_SIMDIR If the simulation files generated by Platform Designer are not in the simulation working directory, use the QSYS_SIMDIR variable to specify the directory location of the Platform Designer simulation files.
QUARTUS_INSTALL_DIR Points to the Quartus installation directory that contains the device family library.

Top-Level Simulation HDL File for a Testbench System

The example below shows the pattern_generator_tb generated for a Platform Designer system called pattern_generator. The top.sv file defines the top-level module that instantiates the pattern_generator_tb simulation model, as well as a custom SystemVerilog test program with BFM transactions, called test_program.

module top();
 pattern_generator_tb tb();
 test_program pgm();
endmodule

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