Intel Quartus Prime Pro Edition User Guide: Third-party Synthesis
Mentor Graphics Precision Synthesis Support
About Precision RTL Synthesis Support
To obtain and license the Precision Synthesis software, refer to the Mentor Graphics website. To install and run the Precision Synthesis software and to set up your work environment, refer to the Precision Synthesis Installation Guide in the Precision Manuals Bookcase. To access the Manuals Bookcase in the Precision Synthesis software, click Help and select Open Manuals Bookcase.
Design Flow
- Create Verilog HDL or VHDL design files.
- Create a project in the Precision Synthesis software that contains the HDL files for your design, select your target device, and set global constraints.
- Compile the project in the Precision Synthesis software.
- Add specific timing
constraints, optimization attributes, and compiler directives to optimize the
design during synthesis. With the design analysis and cross-probing
capabilities of the Precision Synthesis software, you can identify and improve
circuit area and performance issues using prelayout timing estimates.
Note: For best results, Mentor Graphics recommends specifying constraints that are as close as possible to actual operating requirements. Properly setting clock and I/O constraints, assigning clock domains, and indicating false and multicycle paths guide the synthesis algorithms more accurately toward a suitable solution in the shortest synthesis time.
- Synthesize the project in the Precision Synthesis software.
- Create an
Intel®
Quartus® Prime project and import the following files generated by the
Precision Synthesis software into the
Intel®
Quartus® Prime project:
- The Verilog Quartus Mapping File ( .vqm) netlist
- Synopsys Design Constraints File (.sdc) for Timing Analyzer constraints
- Tcl Script Files (.tcl) to set up your Intel® Quartus® Prime project and pass constraints
Note: If your design uses the Classic Timing Analyzer for timing analysis in the Intel® Quartus® Prime software versions 10.0 and earlier, the Precision Synthesis software generates timing constraints in the Tcl Constraints File (.tcl). If you are using the Intel® Quartus® Prime software versions 10.1 and later, you must use the Timing Analyzer for timing analysis. - After obtaining place-and-route results that meet your requirements, configure or program the Intel device.
You can run the Intel® Quartus® Prime software from within the Precision Synthesis software, or run the Precision Synthesis software using the Intel® Quartus® Prime software.
Timing Optimization
You can use other options and techniques in the Intel® Quartus® Prime software to meet area and timing requirements. For example, the WYSIWYG Primitive Resynthesis option can perform optimizations on your EDIF netlist in the Intel® Quartus® Prime software.
While simulation and analysis can be performed at various points in the design process, final timing analysis should be performed after placement and routing is complete.
Intel Device Family Support
Precision Synthesis Generated Files
File Extension |
File Description |
---|---|
.psp |
Precision Synthesis Project File. |
.xdb |
Mentor Graphics Design Database File. |
.rep 1 |
Synthesis Area and Timing Report File. |
.vqm 2 |
Technology-specific netlist in .vqm file format. By default, the Precision Synthesis software creates .vqm files for Arria series, Cyclone series, and Stratix series devices. The Precision Synthesis software defaults to creating .vqm files when the device is supported. |
.tcl |
Forward-annotated Tcl assignments and constraints file. The <project name> .tcl file is generated for all devices. The .tcl file acts as the Intel® Quartus® Prime Project Configuration file and is used to make basic project and placement assignments, and to create and compile a Intel® Quartus® Prime project. |
.acf |
Assignment and Configurations file for backward compatibility with the MAX+PLUS II software. For devices supported by the MAX+PLUS II software, the MAX+PLUS II assignments are imported from the MAX+PLUS II .acf file. |
.sdc |
Intel® Quartus® Prime timing constraints file in Synopsys Design Constraints format. This file is generated automatically if the device uses the Timing Analyzer by default in the Intel® Quartus® Prime software, and has the naming convention <project name> _pnr_constraints .sdc. |
Creating and Compiling a Project in the Precision Synthesis Software
Mapping the Precision Synthesis Design
Mentor Graphics recommends creating an .sdc file and adding this file to the Constraint Files section of the Project Files list. You can create this file with a text editor, by issuing command-line constraint parameters, or by directing the Precision Synthesis software to generate the file automatically the first time you synthesize your design. By default, the Precision Synthesis software saves all timing constraints and attributes in two files: precision_rtl.sdc and precision_tech.sdc. The precision_rtl.sdc file contains constraints set on the RTL-level database (post-compilation) and the precision_tech.sdc file contains constraints set on the gate-level database (post- synthesis) located in the current implementation directory.
You can also enter constraints at the command line. After adding constraints at the command line, update the .sdc file with the update constraint file command. You can add constraints that change infrequently directly to the HDL source files with HDL attributes or pragmas.
Setting Timing Constraints
You also can use multicycle path and false path assignments to relax requirements or exclude nodes from timing requirements, which can improve area utilization and allow the software optimizations to focus on the most critical parts of the design.
For details about the syntax of Synopsys Design Constraint commands, refer to the Precision RTL Synthesis User’s Manual and the Precision Synthesis Reference Manual.
Setting Mapping Constraints
Assigning Pin Numbers and I/O Settings
You can use the set_attribute command in the Precision Synthesis software .sdc file to specify pin number constraints, I/O standards, drive strengths, and slow slew‑rate settings. The table below describes the format to use for entries in the Precision Synthesis software constraint file.
Constraint |
Entry Format for Precision Constraint File |
---|---|
Pin number |
set_attribute -name PIN_NUMBER -value "<pin number>" -port <port name> |
I/O standard |
set_attribute -name IOSTANDARD -value "<I/O Standard>" -port <port name> |
Drive strength |
set_attribute -name DRIVE -value "<drive strength in mA>" -port <port name> |
Slew rate |
set_attribute -name SLEW -value "TRUE | FALSE" -port <port name> |
You also can use synthesis attributes or pragmas in your HDL code to make these assignments.
Verilog HDL Pin Assignment
//pragma attribute clk pin_number P10;
VHDL Pin Assignment
attribute pin_number : string attribute pin_number of clk : signal is "P10";
You can use the same syntax to assign the I/O standard using the IOSTANDARD attribute, drive strength using the attribute DRIVE, and slew rate using the SLEW attribute.
For more details about attributes and how to set these attributes in your HDL code, refer to the Precision Synthesis Reference Manual.
Assigning I/O Registers
For the Stratix series, Cyclone series, and the MAX II device families, the Precision Synthesis software can move an internal register to an I/O register without any restrictions on design hierarchy.
For more mature devices, the Precision Synthesis software can move an internal register to an I/O register only when the register exists in the top-level of the hierarchy. If the register is buried in the hierarchy, you must flatten the hierarchy so that the buried registers are moved to the top-level of the design.
Disabling I/O Pad Insertion
Preventing the Precision Synthesis Software from Adding I/O Pads
To prevent the Precision Synthesis software from adding I/O pads:
- You can use the Precision Synthesis GUI or add the following command to the project file:
setup_design -addio=false
Preventing the Precision Synthesis Software from Adding an I/O Pad on an Individual Pin
To prevent I/O pad insertion on an individual pin when you are using a black box, such as DDR or a phase-locked loop (PLL), at the external ports of the design, perform the following steps:
- Compile your design.
- Use the Precision Synthesis GUI to select the individual pin and turn off I/O pad insertion.
Controlling Fan-Out on Data Nets
To eliminate routability and timing issues associated with high fan-out nets, the Precision Synthesis software also allows you to override the library default value on a global or individual net basis. You can override the library value by setting a max_fanout attribute on the net.
Synthesizing the Design and Evaluating the Results
<project name>_impl_<number>
After synthesis is complete, you can evaluate the results for area and timing. The Precision RTL Synthesis User’s Manual describes different results that can be evaluated in the software.
There are several schematic viewers available in the Precision Synthesis software: RTL schematic, Technology-mapped schematic, and Critical Path schematic. These analysis tools allow you to quickly and easily isolate the source of timing or area issues, and to make additional constraint or code changes to optimize the design.
Obtaining Accurate Logic Utilization and Timing Analysis Reports
Guidelines for Intel FPGA IP Cores and Architecture-Specific Features
If you want to instantiate an IP core such as a PLL in your HDL code, you can instantiate and parameterize the function using the port and parameter definitions, or you can customize a function with the parameter editor. Intel recommends using the IP Catalog and parameter editor, which provides a graphical interface within the Intel® Quartus® Prime software for customizing and parameterizing any available IP core for the design.
The Precision Synthesis software automatically recognizes certain types of HDL code and infers the appropriate IP core.
Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files
Include the hollow-body black box module declaration <output file>_bb.v in your Precision Synthesis project to describe the port connections of the black box. Adding the IP core wrapper file <output file>.v in your Precision Synthesis project is optional, but you must add it to your Intel® Quartus® Prime project along with the Precision Synthesis generated EDIF or VQM netlist.
Alternatively, you can include the IP core wrapper file <output file>.v in your Precision Synthesis project and turn on the Exclude file from Compile Phase option in the Precision Synthesis software to exclude the file from compilation and to copy the file to the appropriate directory for use by the Intel® Quartus® Prime software during place-and-route.
Instantiating IP Cores With IP Catalog-Generated VHDL Files
Adding the IP core wrapper file <output file>.vhd in your Precision Synthesis project is optional, but you must add the file to your Intel® Quartus® Prime project along with the Precision Synthesis-generated EDIF or VQM netlist.
Alternatively, you can include the IP core wrapper file <output file>.v in your Precision Synthesis project and turn on the Exclude file from Compile Phase option in the Precision Synthesis software to exclude the file from compilation and to copy the file to the appropriate directory for use by the Intel® Quartus® Prime software during place-and-route.
Instantiating Intellectual Property With the IP Catalog and Parameter Editor
To create this netlist file, perform the following steps:
- Select the IP function in the IP Catalog.
- Click Next to open the Parameter Editor.
- Click Set Up Simulation, which sets up all the EDA options.
- Turn on the Generate netlist option to generate a netlist for resource and timing estimation and click OK.
- Click Generate to generate the netlist file.
The Intel® Quartus® Prime software generates a file <output file>_syn.v. This netlist contains the “gray box” information for resource and timing estimation, but does not contain the actual implementation. Include this netlist file into your Precision Synthesis project as an input file. Then include the IP core wrapper file <output file>.v|vhd in the Intel® Quartus® Prime project along with your EDIF or VQM output netlist.
The generated “gray box” netlist file, <output file>_syn.v , is always in Verilog HDL format, even if you select VHDL as the output file format.
Instantiating Black Box IP Functions With Generated Verilog HDL Files
The example below shows a sample top-level file that instantiates my_verilogIP.v, which is a simplified customized variation generated by the IP Catalog and Parameter Editor.
Top-Level Verilog HDL Code with Black Box Instantiation of IP
module top (clk, count); input clk; output[7:0] count; my_verilogIP verilogIP_inst (.clock (clk), .q (count)); endmodule // Module declaration // The following attribute is added to create a // black box for this module. module my_verilogIP (clock, q) /* synthesis syn_black_box */; input clock; output[7:0] q; endmodule
Instantiating Black Box IP Functions With Generated VHDL Files
The example below shows a sample top-level file that instantiates my_vhdlIP.vhd, which is a simplified customized variation generated by the IP Catalog and Parameter Editor.
Top-Level VHDL Code with Black Box Instantiation of IP
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY top IS PORT ( clk: IN STD_LOGIC ; count: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END top; ARCHITECTURE rtl OF top IS COMPONENT my_vhdlIP PORT ( clock: IN STD_LOGIC ; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end COMPONENT; attribute syn_black_box : boolean; attribute syn_black_box of my_vhdlIP: component is true; BEGIN vhdlIP_inst : my_vhdlIP PORT MAP ( clock => clk, q => count ); END rtl;
Inferring Intel FPGA IP Cores from HDL Code
For coding style recommendations and examples for inferring technology-specific architecture in Intel devices, refer to the Precision Synthesis Style Guide.
Multipliers
Controlling DSP Block Inference for Multipliers
Value |
Description |
---|---|
ON |
Use only DSP blocks to implement multipliers, regardless of the size of the multiplier. |
OFF |
Use only logic (LUTs) to implement multipliers, regardless of the size of the multiplier. |
AUTO |
Use logic (LUTs) or DSP blocks to implement multipliers, depending on the size of the multipliers. |
Setting the Use Dedicated Multiplier Option
Setting the dedicated_mult Attribute
Setting the dedicated_mult Attribute in Verilog HDL
//synthesis attribute <signal name> dedicated_mult <value>
Setting the dedicated_mult Attribute in VHDL
ATTRIBUTE dedicated_mult: STRING; ATTRIBUTE dedicated_mult OF <signal name>: SIGNAL IS <value>;
The dedicated_mult attribute can be applied to signals and wires; it does not work when applied to a register. This attribute can be applied only to simple multiplier code, such as a = b * c.
Some signals for which the dedicated_mult attribute is set can be removed during synthesis by the Precision Synthesis software for design optimization. In such cases, if you want to force the implementation, you should preserve the signal by setting the preserve_signal attribute to TRUE.
Setting the preserve_signal Attribute in Verilog HDL
//synthesis attribute <signal name> preserve_signal TRUE
Setting the preserve_signal Attribute in VHDL
ATTRIBUTE preserve_signal: BOOLEAN; ATTRIBUTE preserve_signal OF <signal name>: SIGNAL IS TRUE;
Verilog HDL Multiplier Implemented in Logic
module unsigned_mult (result, a, b); output [15:0] result; input [7:0] a; input [7:0} b; assign result = a * b; //synthesis attribute result dedicated_mult OFF endmodule
VHDL Multiplier Implemented in Logic
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY unsigned_mult IS PORT( a: IN std_logic_vector (7 DOWNTO 0); b: IN std_logic_vector (7 DOWNTO 0); result: OUT std_logic_vector (15 DOWNTO 0)); ATTRIBUTE dedicated_mult: STRING; END unsigned_mult; ARCHITECTURE rtl OF unsigned_mult IS SIGNAL a_int, b_int: UNSIGNED (7 downto 0); SIGNAL pdt_int: UNSIGNED (15 downto 0); ATTRIBUTE dedicated_mult OF pdt_int: SIGNAL IS "OFF; BEGIN a_int <= UNSIGNED (a); b_int <= UNSIGNED (b); pdt_int <= a_int * b_int; result <= std_logic_vector(pdt_int); END rtl;
Multiplier-Accumulators and Multiplier-Adders
The Precision Synthesis software detects multiply-accumulators or multiply‑adders in HDL code and infers an ALTMULT_ACCUM or ALTMULT_ADD IP cores so that the logic can be placed in DSP blocks, or the software maps these functions directly to device atoms to implement the multiplier in the appropriate type of logic.
For more information about DSP blocks in Intel devices, refer to the appropriate Intel device family handbook and device-specific documentation. For details about which functions a given DSP block can implement, refer to the DSP Solutions Center on the Altera website.
For more information about inferring multiply-accumulator and multiply‑adder IP cores in HDL code, refer to the Intel Recommended HDL Coding Styles and the Mentor Graphics Precision Synthesis Style Guide.
Controlling DSP Block Inference
You can use the extract_mac attribute to prevent inference of an ALTMULT_ADD or ALTMULT_ACCUM IP cores in a certain module or entity.
Value | Description |
---|---|
TRUE | The ALTMULT_ADD or ALTMULT_ACCUM IP core is inferred. |
FALSE | The ALTMULT_ADD or ALTMULT_ACCUM IP core is not inferred. |
To control inference, use the extract_mac attribute with the appropriate value from the examples below in your HDL code.
Setting the extract_mac Attribute in Verilog HDL
//synthesis attribute <module name> extract_mac <value>
Setting the extract_mac Attribute in VHDL
ATTRIBUTE extract_mac: BOOLEAN; ATTRIBUTE extract_mac OF <entity name>: ENTITY IS <value>;
Using extract_mac, dedicated_mult, and preserve_signal in Verilog HDL
To control the implementation of the multiplier portion of a multiply-accumulator or multiply-adder, you must use the dedicated_mult attribute.
You can use the extract_mac, dedicated_mult, and preserve_signal attributes (in Verilog HDL and VHDL) to implement the given DSP function in logic in the Intel® Quartus® Prime software.
module unsig_altmult_accuml (dataout, dataa, datab, clk, aclr, clken); input [7:0} dataa, datab; input clk, aclr, clken; output [31:0] dataout; reg [31:0] dataout; wire [15:0] multa; wire [31:0] adder_out; assign multa = dataa * datab; //synthesis attribute multa preserve_signal TRUE //synthesis attribute multa dedicated_mult OFF assign adder_out = multa + dataout; always @ (posedge clk or posedge aclr) begin if (aclr) dataout <= 0; else if (clken) dataout <= adder_out; end //synthesis attribute unsig_altmult_accuml extract_mac FALSE endmodule
Using extract_mac, dedicated_mult, and preserve_signal in VHDL
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY signedmult_add IS PORT( a, b, c, d: IN STD_LOGIC_VECTOR (7 DOWNTO 0); result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)); ATTRIBUTE preserve_signal: BOOLEANS; ATTRIBUTE dedicated_mult: STRING; ATTRIBUTE extract_mac: BOOLEAN; ATTRIBUTE extract_mac OF signedmult_add: ENTITY IS FALSE; END signedmult_add; ARCHITECTURE rtl OF signedmult_add IS SIGNAL a_int, b_int, c_int, d_int : signed (7 DOWNTO 0); SIGNAL pdt_int, pdt2_int : signed (15 DOWNTO 0); SIGNAL result_int: signed (15 DOWNTO 0); ATTRIBUTE preserve_signal OF pdt_int: SIGNAL IS TRUE; ATTRIBUTE dedicated_mult OF pdt_int: SIGNAL IS "OFF"; ATTRIBUTE preserve_signal OF pdt2_int: SIGNAL IS TRUE; ATTRIBUTE dedicated_mult OF pdt2_int: SIGNAL IS "OFF"; BEGIN a_int <= signed (a); b_int <= signed (b); c_int <= signed (c); d_int <= signed (d); pdt_int <= a_int * b_int; pdt2_int <= c_int * d_int; result_int <= pdt_int + pdt2_int; result <= STD_LOGIC_VECTOR(result_int); END rtl;
RAM and ROM
The software supports inference for these functions only if the target device family has dedicated memory blocks.
For more information about inferring RAM and ROM IP cores in HDL code, refer to the Precision Synthesis Style Guide.
Mentor Graphics Precision Synthesis Support Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 | Removed reference to obsolete .edf file from "Design Flow" diagram. |
2018.05.07 | 18.0.0 | Corrected trademark symbols on tool names. |
2016.10.31 | 16.1.0 |
|
Date |
Version |
Changes |
---|---|---|
2015.11.02 | 15.1.0 |
|
June 2014 |
14.0.0 |
|
June 2012 |
12.0.0 |
|
November 2011 |
10.1.1 |
|
December 2010 |
10.1.0 |
|
July 2010 |
10.0.0 |
|
November 2009 |
9.1.0 |
|
March 2009 |
9.0.0 |
|
November 2008 |
8.1.0 |
|
May 2008 |
8.0.0 |
|
Synopsys Synplify Support
About Synplify Support
This document covers the following information:
- General design flow with the Synplify and Intel® Quartus® Prime software.
- Synplify software optimization strategies, including timing-driven compilation settings, optimization options, and other attributes.
- Guidelines for use of Quartus Prime IP cores, including guidelines for HDL inference of IP cores.
Design Flow
- Create Verilog HDL (.v) or VHDL (.vhd) design files.
- Set up a project in the Synplify software and add the HDL design files for synthesis.
- Select a target device and add timing constraints and compiler directives in the Synplify software to help optimize the design during synthesis.
- Synthesize the project in the Synplify software.
- Create an
Intel®
Quartus® Prime project and import the following files generated by the
Synplify software into the
Intel®
Quartus® Prime software.
Use the following files for placement and routing, and for performance
evaluation:
- Verilog Quartus Mapping File (.vqm) netlist.
- The Synopsys Constraints Format (.scf) file for Timing Analyzer constraints.
- The .tcl file to set up your
Intel®
Quartus® Prime project and pass constraints.
Note: Alternatively, you can run the Intel® Quartus® Prime software from within the Synplify software.
- After obtaining place-and-route results that meet your requirements, configure or program the Intel device.
Hardware Description Language Support
The HDL Analyst that is included in the Synplify software is a graphical tool for generating schematic views of the technology-independent RTL view netlist (.srs) and technology-view netlist (.srm) files. You can use the Synplify HDL Analyst to analyze and debug your design visually. The HDL Analyst supports cross-probing between the RTL and Technology views, the HDL source code, the Finite State Machine (FSM) viewer, and between the technology view and the timing report file in the Intel® Quartus® Prime software. A separate license file is required to enable the HDL Analyst in the Synplify software. The Synplify Pro and Premier software include the HDL Analyst.
Intel Device Family Support
Tool Setup
Specifying the Intel Quartus Prime Software Version
Specifying Intel® Quartus® Prime Software Version at the Command Line
set_option -quartus_version <version number>
Synplify Software Generated Files
File Extensions |
File Description |
---|---|
.vqm |
Technology-specific netlist in .vqm file format. A .vqm file is created for all Intel device families supported by the Intel® Quartus® Prime software. |
.scf |
Synopsys Constraint Format file containing timing constraints for the Timing Analyzer. |
.tcl |
Forward-annotated constraints file containing constraints and assignments. A .tcl file for the Intel® Quartus® Prime software is created for all devices. The .tclfile contains the appropriate Tcl commands to create and set up an Intel® Quartus® Prime project and pass placement constraints. |
.srs |
Technology-independent RTL netlist file that can be read only by the Synplify software. |
.srm |
Technology view netlist file. |
.acf |
Assignment and Configurations file for backward compatibility with the MAX+PLUS II software. For devices supported by the MAX+PLUS II software, the MAX+PLUS II assignments are imported from the MAX+PLUS II .acf file. |
.srr 3 |
Synthesis Report file. |
Design Constraints Support
After synthesis is complete, do the following steps:
- Import the .vqm netlist to the Intel® Quartus® Prime software for place-and-route.
- Use the .tcl file generated by the Synplify software to forward‑annotate your project constraints including device selection. The .tcl file calls the generated .scf to forward-annotate Timing Analyzer timing constraints.
Running the Intel Quartus Prime Software Manually With the Synplify-Generated Tcl Script
To run the Tcl script to set up your project assignments, perform the following steps:
- Ensure the .vqm, .scf, and .tcl files are located in the same directory.
- In the Intel® Quartus® Prime software, on the View menu, point to and click Tcl Console. The Intel® Quartus® Prime Tcl Console opens.
- At the Tcl Console command prompt, type the following:
source <path>/<project name>_cons.tcl
Passing Timing Analyzer SDC Timing Constraints to the Intel Quartus Prime Software
The Synplify-generated .tcl file contains constraints for the Intel® Quartus® Prime software, such as the device specification and any location constraints. Timing constraints are forward‑annotated in the Synopsys Constraints Format (.scf) file.
The following list of Synplify constraints are converted to the equivalent Intel® Quartus® Prime SDC commands and are forward-annotated to the Intel® Quartus® Prime software in the .scffile:
- define_clock
- define_input_delay
- define_output_delay
- define_multicycle_path
- define_false_path
All Synplify constraints described above are mapped to SDC commands for the Timing Analyzer.
For syntax and arguments for these commands, refer to the applicable topic in this manual or refer to Synplify Help. For a list of corresponding commands in the Intel® Quartus® Prime software, refer to the Intel® Quartus® Prime Help.
Individual Clocks and Frequencies
Input and Output Delay
Multicycle Path
False Path
Simulation and Formal Verification
If area and timing requirements are satisfied, use the files generated by the Intel® Quartus® Prime software to program or configure the Intel device. If your area or timing requirements are not met, you can change the constraints in the Synplify software or the Intel® Quartus® Prime software and rerun synthesis. Intel recommends that you provide timing constraints in the Synplify software and any placement constraints in the Intel® Quartus® Prime software. Repeat the process until area and timing requirements are met.
You can also use other options and techniques in the Intel® Quartus® Prime software to meet area and timing requirements, such as WYSIWYG Primitive Resynthesis, which can perform optimizations on your .vqm netlist within the Intel® Quartus® Prime software.
Synplify Optimization Strategies
For more information about applying attributes, refer to the Synopsys FPGA Synthesis Reference Manual.
Using Synplify Premier to Optimize Your Design
The physical location annotation file is called <design name>_plc.tcl. If you open the Intel® Quartus® Prime software from the Synplify Premier software user interface, the Intel® Quartus® Prime software automatically uses this file for the placement information.
The Physical Analyst allows you to examine the placed netlist from the Synplify Premier software, which is similar to the HDL Analyst for a logical netlist. You can use this display to analyze and diagnose potential problems.
Using Implementations in Synplify Pro or Premier
Timing-Driven Synthesis Settings
The Intel® Quartus® Prime NativeLink feature allows timing constraints that are applied in the Synplify software to be forward-annotated for the Intel® Quartus® Prime software with an .scf file for timing‑driven place and route.
The Synplify Synthesis Report File (.srr) contains timing reports of estimated place‑and-route delays. The Intel® Quartus® Prime software can perform further optimizations on a post-synthesis netlist from third-party synthesis tools. In addition, designs might contain black boxes or intellectual property (IP) functions that have not been optimized by the third-party synthesis software. Actual timing results are obtained only after the design has been fully placed and routed in the Intel® Quartus® Prime software. For these reasons, the Intel® Quartus® Prime post place-and-route timing reports provide a more accurate representation of the design. Use the statistics in these reports to evaluate design performance.
Clock Frequencies
Use the SCOPE window to set global frequency requirements for the entire design and individual clock settings. Use the Clocks tab in the SCOPE window to specify frequency (or period), rise times, fall times, duty cycle, and other settings. Assigning individual clock settings, rather than over‑constraining the global frequency, helps the Intel® Quartus® Prime software and the Synplify software achieve the fastest clock frequency for the overall design. The define_clock attribute assigns clock constraints.
Multiple Clock Domains
Input and Output Delays
Relationship Between tCO and the Output Delay |
---|
tCO = clock period – external output delay |
Relationship Between tSU and the Input Delay |
---|
tSU = clock period – external input delay |
When the syn_forward_io_constraints attribute is set to 1, the Synplify software passes the external input and output delays to the Intel® Quartus® Prime software using NativeLink integration. The Intel® Quartus® Prime software then uses the external delays to calculate the maximum system frequency.
Multicycle Paths
False Paths
FSM Compiler
If the FSM Compiler is turned off, the compiler does not optimize logic as state machines. The state machines are implemented as HDL code. Thus, if the coding style for a state machine is sequential, the implementation is also sequential.
Use the syn_state_machine compiler directive to specify or prevent a state machine from being extracted and optimized. To override the default encoding of the FSM Compiler, use the syn_encoding directive.
Value | Description |
---|---|
Sequential | Generates state machines with the fewest possible flipflops. Sequential, also called binary, state machines are useful for area-critical designs when timing is not the primary concern. |
Gray | Generates state machines where only one flipflop changes during each transition. Gray-encoded state machines tend to be glitches. |
One-hot | Generates state machines containing one flipflop for each state. One-hot state machines typically provide the best performance and shortest clock-to-output delays. However, one-hot implementations are usually larger than sequential implementations. |
Safe | Generates extra control logic to force the state machine to the reset state if an invalid state is reached. You can use the safe value in conjunction with any of the other three values, which results in the state machine being implemented with the requested encoding scheme and the generation of the reset logic. |
Sample VHDL Code for Applying syn_encoding Directive
SIGNAL current_state : STD_LOGIC_VECTOR (7 DOWNTO 0); ATTRIBUTE syn_encoding : STRING; ATTRIBUTE syn_encoding OF current_state : SIGNAL IS "sequential";
By default, the state machine logic is optimized for speed and area, which may be potentially undesirable for critical systems. The safe value generates extra control logic to force the state machine to the reset state if an invalid state is reached.
FSM Explorer in Synplify Pro and Premier
Optimization Attributes and Options
Retiming in Synplify Pro and Premier
Maximum Fan-Out
If you must duplicate an output register or an output enable register, you can create a register for each output pin by using the syn_useioff attribute.
Preserving Nets
Register Packing
Resource Sharing
Preserving Hierarchy
By default, the Synplify software generates a hierarchical .vqm file. To flatten the file, set the syn_netlist_hierarchy attribute to 0.
Register Input and Output Delays
The define_reg_input_delay and define_reg_output_delay options are useful to close timing if your design does not meet timing goals, because the routing delay after placement and routing exceeds the delay predicted by the Synplify software. Rerun synthesis using these options, specifying the actual routing delay (from place‑and‑route results) so that the tool can meet the required clock frequency. Synopsys recommends that for best results, do not make these assignments too aggressively. For example, you can increase the routing delay value, but do not also use the full routing delay from the last compilation.
In the SCOPE constraint window, the registers panel contains the following options:
- Register—Specifies the name of the register. If you have initialized a compiled design, select the name from the list.
- Type—Specifies whether the delay is an input or output delay.
- Route—Shrinks the effective period for the constrained registers by the specified value without affecting the clock period that is forward‑annotated to the Intel® Quartus® Prime software.
Use the following Tcl command syntax to specify an input or output register delay in nanoseconds.
Input and Output Register Delay
define_reg_input_delay {<register>} -route <delay in ns> define_reg_output_delay {<register>} -route <delay in ns>
syn_direct_enable
To use this attribute as a compiler directive to infer registers with clock enables, enter the syn_direct_enable directive in your source code, instead of the SCOPE spreadsheet.
The syn_direct_enable data type is Boolean. A value of 1 or true enables net assignment to the clock-enable pin. The following is the syntax for Verilog HDL:
object /* synthesis syn_direct_enable = 1 */ ;
I/O Standard
The Synplify SDC syntax for the define_io_standard constraint, in which the delay_type must be either input_delay or output_delay.
define_io_standard Constraint
define_io_standard [–disable|–enable] {<objectName>} -delay_type \ [input_delay|output_delay] <columnTclName>{<value>} [<columnTclName>{<value>}...]
For details about supported I/O standards, refer to the Synopsys FPGA Synthesis Reference Manual.
Intel-Specific Attributes
altera_chip_pin_lc
In the SCOPE window, set the value of the altera_chip_pin_lc attribute to a pin number or a list of pin numbers.
You can use VHDL code for making location assignments for supported Intel devices. Pin location assignments for these devices are written to the output .tcl file.
Making Location Assignments in VHDL
ENTITY sample (data_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0); data_out: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); ATTRIBUTE altera_chip_pin_lc : STRING; ATTRIBUTE altera_chip_pin_lc OF data_out : SIGNAL IS "14, 5, 16, 15";
altera_io_powerup
altera_io_opendrain
Guidelines for Intel FPGA IP Cores and Architecture-Specific Features
You can instantiate an IP core in your HDL code with the IP Catalog and configure the IP core with the Parameter Editor, or instantiate the IP core using the port and parameter definition. The IP Catalog and Parameter Editor provide a graphical interface within the Intel® Quartus® Prime software to customize any available Intel FPGA IP core for the design.
The Synplify software also automatically recognizes certain types of HDL code, and infers the appropriate Intel FPGA IP core when an IP core provides optimal results. The Synplify software provides options to control inference of certain types of IP cores.
Instantiating Intel FPGA IP Cores with the IP Catalog
The Synplify software uses the Intel® Quartus® Prime timing and resource estimation netlist feature to report more accurate resource utilization and timing performance estimates, and uses timing-driven optimization, instead of treating the IP core as a “black box.” Including the generated IP core variation wrapper file in your Synplify project, gives the Synplify software complete information about the IP core.
Verify that the correct Intel® Quartus® Prime version is specified in the Synplify software before compiling the generated file to ensure that the software uses the correct library definitions for the IP core. The Quartus Version setting must match the version of the Intel® Quartus® Prime software used to generate the customized IP core.
In addition, ensure that the QUARTUS_ROOTDIR environment variable specifies the installation directory location of the correct Intel® Quartus® Prime version. The Synplify software uses this information to launch the Intel® Quartus® Prime software in the background. The environment variable setting must match the version of the Intel® Quartus® Prime software used to generate the customized IP core.
Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files
Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files
Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores
You might want to change this behavior to reduce run times in the Synplify software, because generating the netlist files can take several minutes for large designs, or if the Synplify software cannot access your Intel® Quartus® Prime software installation to generate the files. Changing this behavior might speed up the compilation time in the Synplify software, but the Quality of Results (QoR) might be reduced.
The Synplify software directs the Intel® Quartus® Prime software to generate information in two ways:
- Some IP cores provide a “clear box” model—the Synplify software fully synthesizes this model and includes the device architecture-specific primitives in the output .vqm netlist file.
- Other IP cores provide a
“gray box” model—the Synplify software reads the resource information, but the
netlist does not contain all the logic functionality.
Note: You need to turn on Generate netlist when using the gray box model. For more information, see the Intel® Quartus® Prime online help.
For these IP cores, the Synplify software uses the logic information for resource and timing estimation and optimization, and then instantiates the IP core in the output .vqm netlist file so the Intel® Quartus® Prime software can implement the appropriate device primitives. By default, the Synplify software uses the clear box model when available, and otherwise uses the gray box model.
Instantiating Intellectual Property with the IP Catalog and Parameter Editor
To create this netlist file, perform the following steps:
- Select the IP core in the IP Catalog.
- Click Next to open the Parameter Editor.
- Click Set Up Simulation, which sets up all the EDA options.
- Turn on the Generate netlist option to generate a netlist for resource and timing estimation and click OK.
- Click Generate to generate the netlist file.
The Intel® Quartus® Prime software generates a file <output file>_syn.v. This netlist contains the gray box information for resource and timing estimation, but does not contain the actual implementation. Include this netlist file in your Synplify project. Next, include the IP core variation wrapper file <output file>.v|vhd in the Intel® Quartus® Prime project along with your Synplify .vqm output netlist.
If your IP core does not include a resource and timing estimation netlist, the Synplify software must treat the IP core as a black box.
Instantiating Black Box IP Cores with Generated Verilog HDL Files
The example shows a top-level file that instantiates my_verilogIP.v, which is a simple customized variation generated by the IP Catalog.
Sample Top-Level Verilog HDL Code with Black Box Instantiation of IP
module top (clk, count); input clk; output [7:0] count; my_verilogIP verilogIP_inst (.clock (clk), .q (count)); endmodule // Module declaration // The following attribute is added to create a // black box for this module. module my_verilogIP (clock, q) /* synthesis syn_black_box */; input clock; output [7:0] q; endmodule
Instantiating Black Box IP Cores with Generated VHDL Files
The example shows a top-level file that instantiates my_vhdlIP.vhd, which is a simplified customized variation generated by the IP Catalog.
Sample Top-Level VHDL Code with Black Box Instantiation of IP
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY top IS PORT ( clk: IN STD_LOGIC ; count: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END top; ARCHITECTURE rtl OF top IS COMPONENT my_vhdlIP PORT ( clock: IN STD_LOGIC ; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end COMPONENT; attribute syn_black_box : boolean; attribute syn_black_box of my_vhdlIP: component is true; BEGIN vhdlIP_inst : my_vhdlIP PORT MAP ( clock => clk, q => count ); END rtl;
Other Synplify Software Attributes for Creating Black Boxes
Adding Timing Models to Black Boxes in Verilog HDL
module ram32x4(z,d,addr,we,clk); /* synthesis syn_black_box syn_tcol="clk->z[3:0]=4.0" syn_tpd1="addr[3:0]->[3:0]=8.0" syn_tsu1="addr[3:0]->clk=2.0" syn_tsu2="we->clk=3.0" */ output [3:0]z; input[3:0]d; input[3:0]addr; input we input clk endmodule
The following additional attributes are supported by the Synplify software to communicate details about the characteristics of the black box module within the HDL code:
- syn_resources—Specifies the resources used in a particular black box.
- black_box_pad_pin—Prevents mapping to I/O cells.
- black_box_tri_pin—Indicates a tri-stated signal.
For more information about applying these attributes, refer to the Synopsys FPGA Synthesis Reference Manual.
Including Files for Intel Quartus Prime Placement and Routing Only
You can also set the option in a script using the -job_owner par option.
The example shows how to define files for a Synplify project that includes a top-level design file, a gray box netlist file, an IP wrapper file, and an encrypted IP file. With these files, the Synplify software writes an empty instantiation of “core” in the .vqm file and uses the gray box netlist for resource and timing estimation. The files core.v and core_enc8b10b.v are not compiled by the Synplify software, but are copied into the place-and-route directory. The Intel® Quartus® Prime software compiles these files to implement the “core” IP block.
Commands to Define Files for a Synplify Project
add_file -verilog -job_owner par "core_enc8b10b.v" add_file -verilog -job_owner par "core.v" add_file -verilog "core_gb.v" add_file -verilog "top.v"
Inferring Intel FPGA IP Cores from HDL Code
Inferring Multipliers
Resource Balancing
Intel devices have a fixed number of DSP blocks, which includes a fixed number of embedded multipliers. If the design uses more multipliers than are available, the Synplify software automatically maps the extra multipliers to logic elements (LEs), or adaptive logic modules (ALMs).
If a design uses more multipliers than are available in the DSP blocks, the Synplify software maps the multipliers in the critical paths to DSP blocks. Next, any wide multipliers, which might or might not be in the critical paths, are mapped to DSP blocks. Smaller multipliers and multipliers that are not in the critical paths might then be implemented in the logic (LEs or ALMs). This ensures that the design fits successfully in the device.
Controlling the DSP Block Inference
Signal Level Attribute
<signal_name> /* synthesis syn_multstyle = "logic" */;
The syn_multstyle attribute applies to wires only; it cannot be applied to registers.
Attribute Name | Value | Description |
---|---|---|
syn_multstyle | lpm_mult | LPM function inferred and multipliers implemented in DSP blocks. |
logic | LPM function not inferred and multipliers implemented as LEs by the Synplify software. | |
block_mult | DSP IP core is inferred and multipliers are mapped directly to DSP block device primitives (for supported devices). |
Signal Attributes for Controlling DSP Block Inference in Verilog HDL Code
module mult(a,b,c,r,en); input [7:0] a,b; output [15:0] r; input [15:0] c; input en; wire [15:0] temp /* synthesis syn_multstyle="logic" */; assign temp = a*b; assign r = en ? temp : c; endmodule
Signal Attributes for Controlling DSP Block Inference in VHDL Code
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity onereg is port ( r : out std_logic_vector (15 downto 0); en : in std_logic; a : in std_logic_vector (7 downto 0); b : in std_logic_vector (7 downto 0); c : in std_logic_vector (15 downto 0); ); end onereg; architecture beh of onereg is signal temp : std_logic_vector (15 downto 0); attribute syn_multstyle : string; attribute syn_multstyle of temp : signal is "logic"; begin temp <= a * b; r <= temp when en='1' else c; end beh;
Inferring RAM
Follow these guidelines for the Synplify software to successfully infer RAM in a design:
- The address line must be at least two bits wide.
- Resets on the memory are not supported. Refer to the device family documentation for information about whether read and write ports must be synchronous.
- Some Verilog HDL statements with blocking assignments might not be mapped to RAM blocks, so avoid blocking statements when modeling RAMs in Verilog HDL.
For some device families, the syn_ramstyle attribute specifies the implementation to use for an inferred RAM. You can apply the syn_ramstyle attribute globally to a module or a RAM instance, to specify registers or block_ram values. To turn off RAM inference, set the attribute value to registers.
When inferring RAM for some Intel device families, the Synplify software generates additional bypass logic. This logic is generated to resolve a half-cycle read/write behavior difference between the RTL and post-synthesis simulations. The RTL simulation shows the memory being updated on the positive edge of the clock; the post-synthesis simulation shows the memory being updated on the negative edge of the clock. To eliminate bypass logic, the output of the RAM must be registered. By adding this register, the output of the RAM is seen after a full clock cycle, by which time the update has occurred, thus eliminating the need for bypass logic.
For devices with TriMatrix memory blocks, disable the creation of glue logic by setting the syn_ramstyle value to no_rw_check. Set syn_ramstyle to no_rw_check to disable the creation of glue logic in dual-port mode.
VHDL Code for Inferred Dual-Port RAM
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; ENTITY dualport_ram IS PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); data_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0) wr_addr, rd_addr: IN STD_LOGIC_VECTOR (6 DOWNTO 0); we: IN STD_LOGIC); clk: IN STD_LOGIC); END dualport_ram; ARCHITECTURE ram_infer OF dualport_ram IS TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECOR (7 DOWNTO 0); SIGNAL mem; Mem_Type; SIGNAL addr_reg: STD_LOGIC_VECTOR (6 DOWNTO 0); BEGIN data_out <= mem (CONV_INTEGER(rd_addr)); PROCESS (clk, we, data_in) BEGIN IF (clk='1' AND clk'EVENT) THEN IF (we='1') THEN mem(CONV_INTEGER(wr_addr)) <= data_in; END IF; END IF; END PROCESS; END ram_infer;
VHDL Code for Inferred Dual-Port RAM Preventing Bypass Logic
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; ENTITY dualport_ram IS PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wr_addr, rd_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0); we : IN STD_LOGIC; clk : IN STD_LOGIC); END dualport_ram; ARCHITECTURE ram_infer OF dualport_ram IS TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL mem : Mem_Type; SIGNAL addr_reg : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL tmp_out : STD_LOGIC_VECTOR (7 DOWNTO 0); --output register BEGIN tmp_out <= mem (CONV_INTEGER (rd_addr)); PROCESS (clk, we, data_in) BEGIN IF (clk='1' AND clk'EVENT) THEN IF (we='1') THEN mem(CONV_INTEGER(wr_addr)) <= data_in; END IF; data_out <= tmp_out; --registers output preventing -- bypass logic generation END IF; END PROCESS; END ram_infer;
RAM Initialization
The examples show how RAM can be initialized through HDL code, and how the corresponding .hex file is generated using Verilog HDL.
Using $readmemb System Task to Initialize an Inferred RAM in Verilog HDL Code
initial begin $readmemb("mem.ini", mem); end always @(posedge clk) begin raddr_reg <= raddr; if(we) mem[waddr] <= data; end
Sample of .vqm Instance Containing Memory Initialization File
altsyncram mem_hex( .wren_a(we),.wren_b(GND),...); defparam mem_hex.lpm_type = "altsyncram"; defparam mem_hex.operation_mode = "Dual_Port"; ... defparam mem_hex.init_file = "mem_hex.hex";
Inferring ROM
Follow these guidelines for the Synplify software to successfully infer ROM in a design:
- The address line must be at least two bits wide.
- The ROM must be at least half full.
- A CASE or IF statement must make 16 or more assignments using constant values of the same width.
Inferring Shift Registers
If necessary, set the implementation style with the syn_srlstyle attribute. If you do not want the components automatically mapped to shift registers, set the value to registers. You can set the value globally, or on individual modules or registers.
For some designs, turning off shift register inference improves the design performance.
Synopsys Synplify Support Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2018.09.24 | 18.1.0 | Removed reference to obsolete .edf file from "Design Flow" diagram. |
2018.05.07 | 18.0.0 | Corrected trademark symbols on tool names. |
2016.10.31 | 16.1.0 |
|
Date |
Version |
Changes |
---|---|---|
2016.05.03 | 16.0.0 |
|
2015.11.02 | 15.1.0 |
|
November 2013 |
13.1.0 |
Dita conversion. Restructured content. |
June 2012 |
12.0.0 |
Removed survey link. |
November 2011 |
10.1.1 |
Template update. |
December 2010 |
10.1.0 |
|
July 2010 |
10.0.0 |
|
November 2009 |
9.1.0 |
|
March 2009 |
9.0.0 |
|
November 2008 |
8.1.0 |
|
May 2008 |
8.0.0 |
|
Intel Quartus Prime Pro Edition User Guides
Refer to the following user guides for comprehensive information on all phases of the Intel® Quartus® Prime Pro Edition FPGA design flow.