Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 1/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Discontinuation of the Intel® HLS Compiler 2. Intel® High Level Synthesis Compiler Pro Edition User Guide 3. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 4. Creating a High-Level Synthesis Component and Testbench 5. Verifying the Functionality of Your Design 6. Optimizing and Refining Your Component 7. Verifying Your IP with Simulation 8. Synthesize your Component IP with Quartus® Prime Pro Edition 9. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
3. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
3.1. High Level Synthesis Design Flow 3.2. The Project Directory
4. Creating a High-Level Synthesis Component and Testbench x
4.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
6. Optimizing and Refining Your Component x
6.1. The High-Level Design Reports
7. Verifying Your IP with Simulation x
7.1. Generation of the Verification Testbench Executable 7.2. Debugging during Verification 7.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
7.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
7.3.1. Execution Model 7.3.2. Comparison of Explicit and Enqueued Function Calls
9. Integrating your IP into a System x
9.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 9.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Discontinuation of the Intel® HLS Compiler
2. Intel® High Level Synthesis Compiler Pro Edition User Guide
3. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
4. Creating a High-Level Synthesis Component and Testbench
5. Verifying the Functionality of Your Design
6. Optimizing and Refining Your Component
7. Verifying Your IP with Simulation
8. Synthesize your Component IP with Quartus® Prime Pro Edition
9. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A. Reviewing the High-Level Design Reports (report.html)

After compiling your component, the Intel® HLS Compiler generates a group of reports and viewers that helps you analyze various component aspects, such as area, loop structure, memory usage, and component pipeline. To launch the High-Level Design Reports, open the following file in a web browser: <result>.prj/reports/report.html.

Section Content
Reviewing the Summary Report
Reviewing Component Architecture
Reviewing Factors That Affect Throughput
Reviewing Component Area Usage
Accessing HLD FPGA Reports in JSON Format

Level Two Title