Intel® High Level Synthesis Compiler Pro Edition: User Guide
ID
683456
Date
1/23/2025
Public
1. Discontinuation of the Intel® HLS Compiler
2. Intel® High Level Synthesis Compiler Pro Edition User Guide
3. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
4. Creating a High-Level Synthesis Component and Testbench
5. Verifying the Functionality of Your Design
6. Optimizing and Refining Your Component
7. Verifying Your IP with Simulation
8. Synthesize your Component IP with Quartus® Prime Pro Edition
9. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
A.3.3. Verification Statistics Report
For each component that the testbench calls, the verification statistics report provides information such as the number and type of invocations, latency, initiation interval, and throughput.
The verification statistics report becomes available after you simulate your component.
Important:
- The data presented in the verification statistics report might be dependent on the input values to the component from the test bench.
- The verification statistics report only reports the component loop initiation interval (II) values and throughput for enqueued invocations. For more details about enqueued invocations, refer to High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls.
The following example verification statistics report is for a component dut that has been run once as a simple function call and 100 times as an enqueued invocation:
For components that use explicit streams, such as ihc::stream_in<> or ihc::stream_out<>, the verification statistics report also provides the throughput for each individual stream, as shown in the details pane:
View the simulation waveform by following the instructions in Debugging during Verification.