Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 4/01/2024
Document Table of Contents

A.5. Accessing HLD FPGA Reports in JSON Format

The high level design report data for the Intel® HLS Compiler Pro Edition is also available as JSON-formatted data.

The JSON files containing the data are available in the <result>.prj/reports/lib/json directory. The directory provides the following .json files:

Table 8.  JSON Files in the <result>.prj/reports/lib/json Directory
File Description
area.json Area Analysis of System
area_src.json Area Analysis of Source (deprecated)
block.json Block View of System Viewer
bottleneck.json Bottleneck View of Loop Analysis Report and Schedule Viewer
info.json Summary of project name, compilation command, versions, and timestamps
loops.json Navigation tree of Loop Analysis report
loops_attr.json Loop Analysis report
mav.json Function View of System Viewer
new_lmv.json Function Memory Viewer
pipeline.json Cluster View of System Viewer
quartus.json Quartus Prime compilation summary
summary.json Component compilation name mapping
system.json System View of System Viewer
tree.json Navigation tree of System Viewer
warnings.json Compilation warning messages
Important: The structure of these JSON files might change from release to release without notice.

You can read the following .json files without a special parser:

  • area.json
  • area_src.json
  • loops.json
  • quartus.json
  • summary.json

For example, if you want to identify all of the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the children section in the loops.json file, as shown below:

“name”:”<block name|Component: component name>  # Find the loops which does not begin with “Component:”
      “data”:[<Yes|No>, <#|n/a>, <II|n/a>]      # The data field corresponds to “Pipelined”, “II”, “Bottleneck”