AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

ID 683437
Date 10/22/2020
Public

2.1. Peripheral and Core RBF are a Matched Pair

Although most of the signal and clock routing information is contained in the core .rbf, some of the routing information for paths between the FPGA core logic to the FPGA I/O pins is in the peripheral .rbf. Therefore, the peripheral .rbf and core .rbf files for a specific build of a design are a matched pair and must be not be mixed with .rbf files from another build.

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