The Intel® Arria® 10 SoC FPGA device supports Early I/O Release. This feature splits the FPGA configuration sequence into two parts. The first part configures the FPGA I/O, the Shared I/O and enables the HPS External Memory Interface (EMIF) if present. The second part of the sequence configures the FPGA fabric.
Splitting the configuration sequence provides HPS access to Shared I/O and EMIF before the FPGA fabric is configured. This allows more flexibility for designs that need faster boot times or alternate boot sources.
Enabling Early I/O Release in an Intel® Arria® 10 SoC FPGA design is optional and adds some pin and usage restrictions. Instructions for enabling and debugging the Early I/O Release feature and usage restrictions are provided in this document.
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