3. Enabling I/O Release
There are multiple steps to enabling the Intel® Arria® 10 SoC FPGA Early I/O Release feature in a design. The feature needs to be enabled in the Intel® Quartus® Prime design project and in the Platform Designer design if using the Intel® Arria® 10 SoC HPS EMIF component. A command line option is also required when converting the design SRAM Object Format (.sof) configuration file to the required .rbf files. You must configure the boot loader to load either just the peripheral .rbf, or both the peripheral and core .rbf files (U-boot is provided below as an example).
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