AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

ID 683437
Date 10/22/2020
Public

1.2. Early I/O Release Flow

When using Early I/O release as part of the FPGA design compilation process, two Raw Binary Format (.rbf) configuration files are generated: a peripheral .rbf file and a core .rbf file. Together, these configuration files contain the same data as a combined configuration .rbf file that is generated when the Early I/O Release feature is not used.

The peripheral .rbf file is loaded first and configures the FPGA I/O, Shared I/O and HPS EMIF. The core .rbf is loaded next and completes the FPGA configuration sequence by configuring the FPGA fabric.

After the peripheral .rbf is successfully loaded, the Intel® Arria® 10 SoC FPGA HPS EMIF pins are released and the interface begins calibration.

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