1.1. Early I/O Release Use Cases
There are a few different reasons why you might choose to enable the Early I/O Release feature of the Intel® Arria® 10 SoC FPGA device. The typical reason is to speed up system boot and configuration time. By gaining early access to a large pool of system RAM connected the HPS EMIF interface, the boot software can more efficiently load the bulk of the FPGA configuration image from mass storage. Restricting boot code to on-chip RAM typically impedes bulk transfers because of the limited code and buffer space.
Figure 1. Early I/O Release
Some designers might want to boot the HPS operating system (OS) immediately. This action can be accomplished by postponing FPGA fabric configuration until the OS has booted. Booting the OS quickly is achieved by using the boot loader to only configure the FPGA I/O, Shared I/O and external memory before FPGA fabric is configured, then allowing the OS to boot and configure the FPGA fabric.
Figure 2. Early I/O Release allows FPGA fabric image to be accessed through a Shared I/O Interface
Another reason to enable the Early I/O Release feature is to gain boot software access to an interface connected to Shared I/O, such as a secondary mass storage device or network connection. This secondary access allows the primary storage connected to the HPS dedicated I/O pins to be smaller and possibly even write protected.