3.2. Platform Designer Component Settings
Early I/O Release is enabled by setting an option in the Intel® Arria® 10 HPS EMIF component. This option is set using the Platform Designer design tool.
Open the Intel® Arria® 10 HPS EMIF component and ensure that the option in the tab is checked.window for the
Selecting this option parameter in the Intel® Arria® 10 HPS EMIF disables the component reset signal from the FPGA core logic. Setting this option is important to ensure that the EMIF does not accidentally reset when loading the FPGA core image.
When not using the Early I/O Release feature, the Intel® Arria® 10 HPS EMIF component is held in reset until the FPGA core is fully configured. However, when using the Early I/O Release feature, the EMIF is released from reset before the FPGA core is configured. This option disables any connection from the FPGA core logic to the EMIF reset.
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