AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

ID 683437
Date 10/22/2020
Public

2. Design Restrictions

There are design restrictions when enabling the Intel® Arria® 10 SoC FPGA Early I/O Release feature. You must evaluate these restrictions during the design planning process. These restrictions should also be considered before you attempt to enable the feature for an existing design to avoid unnecessary design debug effort.

Did you find the information on this page useful?

Characters remaining:

Feedback Message