AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

ID 683437
Date 12/15/2022

2.2. EMIF Pin Usage Restrictions

The FPGA I/O bank lanes released for use by the EMIF are limited to the minimum required based on the external memory interface configuration. All pins used by the EMIF interface must be placed within these bank lanes. For example, no EMIF pins, including CLK or RZQ pins, should be placed in the 2I bank if the interface width is not 64-bits wide. Furthermore, no EMIF pins should be placed in bank 2J, lanes 2 and 3, if the interface is 16-bits wide.

Placing Intel® Arria® 10 SoC FPGA HPS EMIF pins in bank lanes that are not activated by the Early I/O Release feature will fail to calibrate. A design that violates this restriction may pass calibration when the Early I/O Release feature is disabled, and fail only when the feature is enabled. The Platform Designer tools flag this condition as a warning when building with the Early I/O Release feature disabled, and escalates this condition to an error when building with the feature enabled.

Figure 3.  Intel® Arria® 10 SoC EMIF Pin Options