H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.5.5. TX Pause Request

Offset: 0x606

TX Pause Request Fields

Bit Name Description Access Reset
8:0 req_pause Request TX PAUSE or TX PFC.

Bits [7:0]: For PFC

Bit [8]: For PAUSE

Set to request the transmission of TX Pause frames

Works the same way as the corresponding tx_pause port or tx_pfc port

RW 0x0