H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.1.22. Local Transceiver TX EQ 1 Settings for Lane 0

Provides the following Local TX EQ 1 Settings for Lane 0
  • Local TX EQ VOD Setting for Lane 0
  • Local TX EQ Post-Tap Setting for Lane 0
  • Local TX EQ Pre-Tap Setting for Lane 0

Offset: 0xD5

Access: RO

Local Transceiver TX EQ 1 Settings for Lane 0 Fields

Bit Name Description Access Reset
20:16 lt_pretap_setting_ln0 Local TX EQ Pre-tap Setting for Lane 0

This register returns the most recent Pre-tap setting that was written to the local transceiver

RO 0x0
13:8 lt_posttap_setting_ln0 Local TX EQ Post-tap Setting for Lane 0

This register returns the most recent Post-tap setting that was written to the local transceiver .

RO 0x0
4:0 lt_vod_setting_ln0 Local TX EQ VOD Setting for Lane 0

This register returns the most recent VOD setting that was written to the local transceiver

RO 0x0