H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.2.10. Reset Registers

Reset bits:
  • TX MAC reset
  • TX PCS reset
  • RX MAC reset
  • RX PCS reset

Offset: 0x325

Access: RW

Reset Register Fields

Bit Name Description Access Reset
19 rx_pcs_in_rst Reset RX PCS
  • 1: Reset RX PCS
  • Defaults to 0 after power up and i_csr_rst_n
RW 0x1
18 rx_mac_in_rst Reset RX MAC
  • 1: Reset RX MAC
  • Does not reset RX MAC statistics
  • Defaults to 0 after power up and i_csr_rst_n
RW 0x1
17 tx_pcs_in_rst Reset TX PCS
  • 1: Reset TX PCS
  • Defaults to 0 after power up and i_csr_rst_n
RW 0x1
16 tx_mac_in_rst Reset TX MAC
  • 1: Reset TX MAC
  • Does not reset TX MAC statistics
  • Defaults to 0 after power up and i_csr_rst_n
RW 0x1