H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.6.22. TX Pause frame with CRC error (upper 32 bits)

TX Pause frame with CRC error

Number of PAUSE (Standard Flow Control) frames that are malformed CRC is not checked, it is assumed correct at TX

Offset: 0x815

TX Pause frame with CRC error (upper 32 bits) Fields

Bit Name Description Access Reset
31:0 stats_pcnt6 Statistics word

4 bytes of an 8 byte EHIP Statistics

RO 0x0