H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.6.51. TX Pause frames without error (lower 32 bits)

TX Pause frames without error

Number of PAUSE (Standard Flow Control) frames without error

Offset: 0x832

TX Pause frames without error (lower 32 bits) Fields

Bit Name Description Access Reset
31:0 stats_pcnt6 Statistics word

4 bytes of an 8 byte EHIP Statistics

RO 0x0