H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.5.15. Higher 2 bytes of the Source address for Flow Control frames

Offset: 0x610

Higher 2 bytes of the Source address for Flow Control frames Fields

Bit Name Description Access Reset
15:0 saddrh Higher 2 bytes of the Flow control Source Address
Higher 2 bytes of the 6 byte source address used for SFC and PFC frames
  • At power-on, saddrh is set to 16'hE100
  • After i_csr_rst_n is asserted, saddrh is set to the value given by module parameter tx_pause_saddr[47:32]
RW 0xE100