H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

B.5.39. Higher 2 bytes of the Destination address for RX Pause Frames

Offset: 0x708

Higher 2 bytes of the Destination address for RX Pause Frames Fields

Bit Name Description Access Reset
15:0 rx_pause_daddrh Higher bytes of the RX Flow Control Destination Address
Higher 2 bytes of the 6 byte destination address that must be found in incoming SFC and PFC frames
  • This feature requires EHIP to be in a mode with the MAC turned on
  • When this setting is changed, the RX MAC must be reset
  • At power-on, this register defaults to 16'h0180
  • When i_csr_rst_n is asserted, this register is set to the value given by the module parameter rx_pause_daddr[47:32]
RW 0x00000180