Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 9/23/2022
Public

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11.4.1.5. Mapping HLS Data Types to RTL Signals

All supported composite data types are represented by wide input or output signals. Typically, the components of a composite data type are presented with the first-declared value or value of lowest index in the low-order bits of the signal.

Streams

Stream objects are passed by value to the RTL function. The attributes specified for the STREAM element in the Object Manifest File XML should match the template arguments in the you component code.

Your RTL code must use signal names based on the port attribute defined for the STREAM element as follows:
  • <port>_data

    Signal for the data passed on the stream. This signal must be an input signal for direction="in" and and output signal for direction="out".

    The width of this signal must match the width attribute in the STREAM element.

  • <port>_valid

    Used only if usesValid="yes" is set in the STREAM element in the XML file.

    This signal is a single-bit signal for the valid signal.

    If direction="in", this signal is an input signal. If direction="out", this is an output signal.

  • <port>_ready

    Used only if usesReady="yes" is set in the STREAM element in the XML file.

    This signal is a single-bit signal for the ready signal.

    If direction="in", this signal is an input signal. If direction="out", this is an output signal.

  • <port>_empty

    Used only if usesEmpty="yes" is set in the STREAM element in the XML file.

    This signal is a single-bit signal for the empty signal.

    If direction="in", this signal is an input signal. If direction="out", this is an output signal.

  • <port>_startofpacket

    Used only if usesPackets="yes" is set in the STREAM element in the XML file.

    This signal is a single-bit signal to indicated the start of a packet.

    If direction="in", this signal is an input signal. If direction="out", this is an output signal.

  • <port>_endofpacket

    Used only if usesPackets="yes" is set in the STREAM element in the XML file.

    This signal is a single-bit signal to indicated the end of a packet.

    If direction="in", this signal is an input signal. If direction="out", this is an output signal.

These signal names align with stream object input interface parameter names. For details about stream input interface parameters in your component, see Intel HLS Compiler Pro Edition Streaming Input Interfaces.

Arrays

In C++, arrays are passed as a pointer to the memory in which the array is stored.

The Intel® HLS Compiler does not support pointer parameters for RTL modules. However, C++ allows you to pass a struct by value, so you can declare a struct data type that has an array as one of its members and declare your function to accept an argument of this struct-type by value.

Structs

You can use both packed and unpacked structs as call arguments and return values in your HLS components and tasks. The members of a struct are presented as slices of the input signal, with the first-declared struct member in the lowest-order bits of the input signal.
  • Unpacked Structs

    When your struct declaration is not packed, the layout of the input signal corresponding to the struct data type is determined by C language-specific padding rules that cause the Intel® HLS Compiler to insert padding bytes before struct members that require a specific alignment.

    You should use packed structs as arguments to your RTL modules unless there is a specific reason to conform to a particular padded struct layout.

  • Packed Structs

    If the struct type is declared as packed, member values start on an 8-bit boundary.

    The Intel® HLS Compiler does not insert padding bytes to align struct members on platform-defined boundaries. The second-declared member always starts in the next highest byte after high-order byte of the first-declared struct member.

  • System Verilog Structs

    If you are developing an RTL module in System Verilog, you can declare a System Verilog struct type that corresponds to the C++ struct type that is mapped to the input signal of your RTL module.

    The declaration order of the struct members is reversed in the System Verilog declaration because it specifies how the member signals should be concatenated to produce the composite signal. In a System Verilog concatenation expression, the bits are specified from high to low. That is, the last byte of the C++ struct type must be listed first in the System Verilog signal concatenation.

    You can compile your emulation models as HLS components to obtain an interface_structs.v file that contains declarations of the System Verilog struct types corresponding to the struct-type arguments of those functions. For details, see the following tutorial:

    <quartus_installdir>/hls/examples/tutorials/libraries/rtl_struct_mapping

  • Pointers in Structs

    You cannot use struct types that have reference or pointer members as arguments to or return values from RTL-based functions.

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