Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 9/23/2022
Public

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11.4.1.2.1. RTL Module Interface Signals

The Intel® HLS Compiler expects the RTL module to support a single interface with readyLatency = 0, at both input and output.

As shown in RTL Module Interfaces, the RTL module must have four ports:
  • ivalid and iready as the input ready/valid interface
  • ovalid and oready as the output ready/valid interface
The following figure illustrates the timing diagram for input data transfer with back pressure.
Figure 21. Timing Diagram for Input and Output Data Transfer with Back Pressure

For an RTL module with a fixed latency, the output signals (ovalid and oready) can have constant high values, and the input ready signal (iready) can be ignored.

A stall-free RTL module might receive an invalid input signal (ivalid is low). In this case, the module ignores the input and produces invalid data on the output. For a stall-free RTL module without an internal state, it might be easier to propagate the invalid input through the module. However, for an RTL module with an internal state, you must handle an ivalid = 0 input carefully.

Example Timing Diagram of a Stall-free RTL Component

Consider the following example timing diagram of a stall-free RTL component:

Figure 22. Timing Diagram of a Stall-free RTL Component
For this component, the following ATTRIBUTE elements are set in the object manifest file for the RTL module:
  • IS_STALL_FREE value = "yes"
  • IS_FIXED_LATENCY value = "yes"
  • EXPECTED_LATENCY value = "2"

Example Timing Diagram of a Non-stall-free RTL Component

Consider the following example timing diagram of a non-stall-free RTL component:

Figure 23. Timing Diagram of a Non-stall-free RTL Component
For this component, the following ATTRIBUTE elements are set in the object manifest file for the RTL module:
  • IS_STALL_FREE value = "no"
  • IS_FIXED_LATENCY value = "no"
  • EXPECTED_LATENCY value = "4"

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