Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 9/23/2022

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Document Table of Contents Integration of an RTL Module into the HLS Pipeline

When you specify an HLS library during component compilation, the Intel® HLS Compiler integrates the RTL module within the library into the overall component pipeline.
The following figure shows how an HLS library called myMod might be integrated into the example pipeline described in Intel HLS Compiler Hardware Model.
Figure 20. Example of Pipeline Architecture That Integrates an HLS Library

The depicted RTL module has a latency of 3 cycles. Since the multiply and add operations have a latency of just one cycle, the compiler inserts buffering to balance the latency of the parallel data paths in the pipeline. A balanced latency allows the invocations of the HLS component to execute without stalling the pipeline.

Specifying the latency of the RTL module in the HLS library object manifest file allows the HLS compiler to balance the pipeline latencies in the HLS component. The pipeline integration protocol uses ready/valid handshaking, so the latency of the RTL module can be variable. However, the variability in the latency should be small to maximize performance. In addition, specify the latency in the HLS library object manifest file for the object in the HLS library so that the RTL module experiences a good approximation of the actual latency in steady state.

Note: You must specify the RTL module latency correctly in the HLS library object manifest file, or you get bad quality of results (QoR) for your component.

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