Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 9/23/2022
Public

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4.2. Avalon® Streaming Interfaces

A component can have input and output streams that conform to the Avalon Streaming (ST) interface specifications. These input and output streams are represented by passing references to ihc::stream_in<> and ihc::stream_out<> objects as function arguments to the component.

When you use an Avalon ST interface, you can serialize the data over several clock cycles. That is, one component invocation can read from a stream multiple times.

You cannot derive new classes from the stream classes or encapsulate them in other formats such as structs or arrays. However, you may use references to instances of these classes as references inside other classes, meaning that you can create a class that has a reference to a stream object as a data member.

A component can have multiple read sites for a stream. Similarly, a component can have multiple write sites for a stream. However, for best component performance try to restrict each input stream in your design to a single read site and each output stream to a single write site.

Note: Within the component, there is no guarantee on the order of execution of different streams unless a data dependency exists between streams.
For more information about streaming interfaces, refer to "Avalon Streaming Interfaces" in Avalon Interface Specifications.
Restriction: The Intel® HLS Compiler does not support the Avalon ST channel or error signals.

Streaming Input Interfaces

Table 8.   Intel® HLS Compiler Pro Edition Streaming Input Interface Template Summary
Template Object or Parameter Description
ihc::stream_in Streaming input interface to the component.
ihc::buffer Specifies the capacity (in words) of the FIFO buffer on the input data that associates with the stream.
ihc::readyLatency Specifies the number of cycles between when the ready signal is deasserted and when the input stream can no longer accept new inputs.
ihc::bitsPerSymbol Describes how the data is broken into symbols on the data bus.
ihc::firstSymbolInHighOrderBits Specifies whether the data symbols in the stream are in big endian order.
ihc::usesPackets Exposes the startofpacket and endofpacket sideband signals on the stream interface.
ihc::usesEmpty

Exposes the empty out-of-band signal on the stream interface.

ihc::usesValid Controls whether a valid signal is present on the stream interface.
Table 9.   Intel® HLS Compiler Pro Edition Streaming Input Interface stream_in Function APIs
Function API Description
T read() Blocking read call to be used from within the component
T read(bool& sop, bool& eop)

Available only if usesPackets<true> is set.

Blocking read with out-of-band startofpacket and endofpacket signals.
T read(bool& sop, bool& eop, int& empty) Available only if usesPackets<true> and usesEmpty<true> are set.

Blocking read with out-of-band startofpacket, endofpacket, and empty signals.

T tryRead(bool &success) Non-blocking read call to be used from within the component. The success bool is set to true if the read was valid. That is, the Avalon® -ST valid signal was high when the component tried to read from the stream.

The emulation model of tryRead() is not cycle-accurate, so the behavior of tryRead() might differ between emulation and simulation.

T tryRead(bool& success, bool& sop, bool& eop)

Available only if usesPackets<true> is set.

Non-blocking read with out-of-band startofpacket and endofpacket signals.
T tryRead(bool& success, bool& sop, bool& eop, int& empty) Available only if usesPackets<true> and usesEmpty<true> are set.

Non-blocking read with out-of-band startofpacket, endofpacket, and emptysignals.

void write(T data) Blocking write call to be used from the testbench to populate the FIFO to be sent to the component.
void write(T data, bool sop, bool eop)

Available only if usesPackets<true> is set.

Blocking write call with out-of-band startofpacket and endofpacket signals.
void write(T data, bool sop, bool eop, int empty) Available only if usesPackets<true> and usesEmpty<true> are set.

Blocking write call with out-of-band startofpacket, endofpacket, and empty signals.

Streaming Output Interfaces

Table 10.   Intel® HLS Compiler Pro Edition Streaming Output Interface Template Summary
Template Object or Parameter Description
ihc::stream_out Streaming output interface from the component.
ihc::readylatency Specifies the number of cycles between when the ready signal is deasserted and when the input stream can no longer accept new inputs.
ihc::bitsPerSymbol Describes how the data is broken into symbols on the data bus.
ihc::firstSymbolInHighOrderBits Specifies whether the data symbols in the stream are in big endian order.
ihc::usesPackets Exposes the startofpacket and endofpacket sideband signals on the stream interface.
ihc::usesEmpty

Exposes the empty out-of-band signal on the stream interface.

ihc::usesReady Controls whether a ready signal is present.
Table 11.   Intel® HLS Compiler Pro Edition Streaming Output Interface stream_out Function APIs
Function API Description
void write(T data) Blocking write call from the component
void write(T data, bool sop, bool eop)

Available only if usesPackets<true> is set.

Blocking write with out-of-band startofpacket and endofpacket signals.
void write(T data, bool sop, bool eop, int empty) Available only if usesPackets<true> and usesEmpty<true> are set.

Blocking write with out-of-band startofpacket, endofpacket, and empty signals.

bool tryWrite(T data) Non-blocking write call from the component. The return value represents whether the write was successful.
bool tryWrite(T data, bool sop, bool eop)

Available only if usesPackets<true> is set.

Non-blocking write with out-of-band startofpacket and endofpacket signals.

The return value represents whether the write was successful. That is, the downstream interface was pulling the ready signal high while the HLS component tried to write to the stream.

bool tryWrite(T data, bool sop, bool eop, int empty) Available only if usesPackets<true> and usesEmpty<true> are set.

Non-blocking write with out-of-band startofpacket, endofpacket, and empty signals. The return value represents whether the write was successful.

T read() Blocking read call to be used from the testbench to read back the data from the component
T read(bool &sop, bool &eop)

Available only if usesPackets<true> is set.

Blocking read call to be used from the testbench to read back the data from the component with out-of-band startofpacket and endofpacket signals.
T read(bool &sop, bool &eop, int &empty) Available only if usesPackets<true> and usesEmpty<true> are set.

Blocking read call to be used from the testbench to read back the data from the component with out-of-band startofpacket, endofpacket, and empty signals.

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