Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 9/23/2022
Public

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13.9. Intel® HLS Compiler Pro Edition Component Attributes

Table 45.   Intel® HLS Compiler Component Attributes Summary
Attribute Description
hls_component_ii Force the component to which you apply this attribute to have a specified component initiation interval (II).
hls_disable_component_pipelining Prevents the creation of the pipelined component datapath. Multiple invocations of this component now occur sequentially and not simultaneously.
hls_max_concurrency Request more copies of the component memory so that the component can run multiple invocations in parallel.
hls_scheduler_target_fmax_mhz Specify the target clock frequency of your component.
hls_use_stall_enable_clusters Group related operations into stall-enabled clusters to try to improve latency and area usage while possibly sacrificing throughput, when compared to the default stall-free clustering implementation.

hls_component_ii Component Attribute

Syntax
hls_component_ii(<N>)
Description
Forces the component to which you apply this attribute to have a component initiation interval (II) of <N>, where <N> is a positive integer value.

This can have an adverse effect on the fMAX of your component because using this attribute to get a lower II combines pipeline stages together and creates logic with a long propagation delay.

Using this attribute with a larger II inserts more pipeline stages and can give you a better component fMAX value.

hls_disable_component_pipelining Component Attribute

Syntax
hls_disable_component_pipelining
Description
Tells the compiler to not create a pipelined datapath for the component. An unpipelined component datapath can save FPGA area utilization in some cases.

Use this attribute when a pipelined datapath does not improve your component throughput or when the component is not invoked repeatedly.

Example
#include "HLS/hls.h"

hls_disable_component_pipelining
component void baz ( /* arguments */ ){
  // component code
}

hls_max_concurrency Component Attribute

Syntax
hls_max_concurrency(<N>)
Description
In some cases, the concurrency of a component is limited to 1. This limit occurs when the generated hardware cannot be shared across component invocations. For example, when using component memories for a non-static variable.

You can use this attribute to request more copies of the component memory so that the component can run multiple invocations in parallel.

This attribute can accept any non-negative whole number, including 0.
Value greater than 0
A value greater than 0 indicates how many copies of the component memory to instantiate as well as how many component invocations can be in flight at once.
Value equal to 0
Setting hls_max_concurrency to a value of 0 is useful in cases when there is no component memory but the component still has a poor dynamic loop initiation interval (II) even if you believe your component II should be 1. You can review the II for loops in your component in the high level design report.

To learn more, review the design example: <quartus_installdir>/hls/examples/inter_decim_filter.

Example
hls_max_concurrency(2)
component void foo(ihc::stream_in<int> &data_in,
      ihc::stream_out<int> &data_out) {
 int arr[N];
 for (int i = 0; i < N; i++) {
   arr[i] = data_in.read();
 }
 // Operate on the data and modify in place
 for (int i = 0; i < N; i++) {
   data_out.write(arr[i]);
 }
}

hls_scheduler_target_fmax_mhz Component Attribute

Syntax
hls_scheduler_target_fmax_mhz(<N>)
Description
Apply the hls_scheduler_target_fmax_mhz component attribute to have the compiler target a specific fMAX value. Specify the target fMAX value in MHz.

The component is not guaranteed to close timing at the specified frequency, and any tasks in a system of tasks use the same clock regardless of having different scheduling targets.

hls_use_stall_enable_clusters Component Attribute

Syntax
hls_use_stall_enable_clusters
Description
Apply the hls_use_stall_enable component attribute to reduce the area of your component while possibly decreasing your component fMAX and throughput.

The Intel® HLS Compiler typically groups related operations into clusters. In many cases, the clusters are stall-free clusters. A stall-free cluster executes the operations without any stalls and contains a FIFO at the end of the cluster that holds the results if the cluster is stalled. This FIFO adds area and latency to the component, but might allow a higher fMAX and increased throughput.

If you prefer lower FPGA area usage and lower latency over higher throughput, use the hls_use_stall_enable component attribute to bias the compiler to produce stall-enabled clusters. Stall-enabled clusters lack the FIFO, which reduces area and latency, but pass stall signals to the contained operations.

Passing stall signals might reduce fMAX.

Not all operations support stall, and these operations cannot be contained in a stall-enabled cluster. The compiler generates a warning if some operations cannot be placed into a stall-enabled cluster.

The compiler automatically uses stall-enabled clusters for HLS components if it can determine that stall-enable is always beneficial. This attribute requests the compiler to form stall-enabled clusters if possible.

Intel Agilex and Stratix 10 Restriction: This attribute does not apply to designs that target Intel® Agilex™ or Intel® Stratix® 10 devices unless you specify the --hyper-optimized-handshaking=off option of the Intel® HLS Compiler i++ command.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/stall_enable

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