H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683314
Date 1/27/2021
Document Table of Contents

1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench

Figure 5. Procedure

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench sends ten or fourteen packets, receives the same number of packets, and displays "Testbench complete."
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    Mentor Graphics ModelSim* In the command line, type vsim -do run_vsim.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do

    Note: The ModelSim* - Intel® FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim* SE.
    Cadence NCSim In the command line, type sh run_ncsim.sh
    Synopsys VCS*/VCS MX* In the command line, type sh run_vcs.sh or sh run_vcsmx.sh
    Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.
    Xcelium* In the command line, type sh run_xcelium.sh

The successful test run displays output confirming the following behavior:

  1. Waiting for the ATX PLLs to lock.
  2. Waiting for RX transceiver reset to complete.
  3. Waiting for RX alignment.
  4. Sending ten (MAC+PCS, OTN, and FlexE) or hundred (PCS Only) packets.
  5. Receiving those packets (MAC+PCS, OTN, and FlexE) or receiving and checking those packets (PCS Only).
  6. Displaying Testbench complete.