H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

1.5. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
    Note: The hardware design example in Intel® Quartus® Prime version 19.1 supports only MAC+PCS and PCS Only variants.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/alt_ehip2.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware design example on the Intel® Stratix® 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select the Stratix 10 MX FPGA Development Kit to which your Intel® Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel® Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
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