H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683314
Date 1/27/2021
Public
Document Table of Contents

2. Design Example Description

The design example demonstrates the basic functions of the H-Tile Hard IP for Ethernet Intel FPGA IP core with the following variants:
  • 100 Gbps datarate:
    • MAC + PCS
    • PCS Only
    • OTN
    • FlexE
Note: The hardware design example in Intel® Quartus® Prime version 20.2 supports only MAC+PCS and PCS Only variants.
Note: The H-Tile Hard IP for Ethernet Intel FPGA IP provides preliminary support for the OTN feature. For further inquiries, contact your nearest Intel sales representative or file an Intel Premier Support (IPS) case on https://www.intel.com/content/www/us/en/programmable/my-intel/mal-home.html.
You can generate the design from the Example Design tab in the H-Tile Hard IP for Ethernet Intel FPGA parameter editor.

To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench, compilation-only, and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.

Note: The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment. You must perform more extensive verification of your own H-Tile Hard IP for Ethernet Intel FPGA design in simulation and in hardware.