H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

1.1. Directory Structure

Figure 2.  H-Tile Hard IP for Ethernet Intel FPGA Design Example Directory Structure

The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design. The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench. The compilation-only design example is located in <design_example_dir>/compilation_test_design.

Table 1.   H-Tile Hard IP for Ethernet Intel FPGA IP Core Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

run_vsim.do

The Mentor Graphics ModelSim* script to run the testbench.

run_vcs.sh

The Synopsys VCS* script to run the testbench.

run_vcsmx.sh The Synopsys VCS MX* script (combined Verilog HDL and System Verilog with VHDL) to run the testbench.
run_ncsim.sh

The Cadence NCSim* script to run the testbench.

run_xcelium.sh The Xcelium* script to run the testbench.
Table 2.   H-Tile Hard IP for Ethernet Intel FPGA IP Core Hardware Design Example File Descriptions

File Names

Description

alt_ehip2.qpf Intel® Quartus® Prime project file
alt_ehip2.qsf Intel® Quartus® Prime project settings file
alt_ehip2.sdc Synopsys Design Constraints files. You can copy and modify these files for your own H-Tile Hard IP for Ethernet Intel FPGA design.
alt_ehip2.v Top-level Verilog HDL design example file
common/ Hardware design example support files
hwtest/main.tcl

Main file for accessing System Console
Level Two Title