H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example

Figure 6.  H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example Block Diagram

The testbench sends traffic through the IP core, exercising the transmit and receive MAC client interfaces of the IP core.

The simulation design example instantiates a main ATX PLL for transceiver channel 0 and 1, and a clock buffer for channel 2 and 3.

The testbench in this design example performs the following:
  1. The client logic resets the IP core.
  2. Client logic waits for RX datapath to align.
  3. Once alignment is complete, client logic transmits a series of packets to the IP core.
  4. The client logic receives the same series of packets through RX MAC interface.
  5. The client logic then checks the number of packets received and verifies that the packets have no errors.
The following sample output illustrates a successful simulation test run for a 100 Gbps, MAC+PCS IP core variation. Times are in picoseconds. 
Ref clock is 644.53125 MHz

================================================
Module ct1_hssi_cr2_ehip_pcs_interface
================================================
silicon_rev = 14nm5bcr2ea

waiting for o_tx_lanes_stable...
o_tx_lanes_stable is 1 at time                525000
waiting for tx_dll_lock....
TX DLL LOCK is 1 at time              25332363
waiting for tx_transfer_ready....
TX transfer ready is 1 at time              25652235
waiting for rx_transfer_ready....
RX transfer ready is 1 at time              31979703
EHIP PLD Ready out is 1 at time              32040000
EHIP reset out is 0 at time              32304000
EHIP reset ack is 0 at time              32612783
EHIP TX reset out is 0 at time              32928000
EHIP TX reset ack is 0 at time              82562795
waiting for EHIP Ready....
EHIP READY is 1 at time              82629435
EHIP RX reset out is 0 at time              82968000
waiting for rx reset ack....
EHIP RX reset ack is 0 at time              83029275
Waiting for RX Block Lock
EHIP RX Block Lock  is high at time              90223063
Waiting for AM lock
EHIP RX AM Lock  is high at time              91172683
Waiting for RX alignment
RX deskew locked
RX lane aligmnent locked
TX enabled
** Sending Packet           1...
** Sending Packet           2...
** Sending Packet           3...
** Sending Packet           4...
** Sending Packet           5...
** Sending Packet           6...
** Received Packet          1...
** Sending Packet           7...
** Received Packet          2...
** Sending Packet           8...
** Received Packet          3...
** Sending Packet           9...
** Received Packet          4...
** Sending Packet          10...
** Received Packet          5...
** Received Packet          6...
** Received Packet          7...
** Received Packet          8...
** Received Packet          9...
** Received Packet         10...
**
** Testbench complete.
**
*****************************************
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