H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example

Figure 7.  H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example Block Diagram

The testbench sends traffic through the IP core, exercising the transmit and receive Media Independent Interface (MII) of the IP core.

The simulation design example instantiates a main ATX PLL for transceiver channel 0 and 1, and a clock buffer for channel 2 and 3.

The testbench in this design example performs the following:

  1. The client logic resets the IP core.
  2. Client logic waits for RX datapath to align.
  3. Once alignment is complete, client logic transmits a series of packets to the IP core through TX MII interface.
  4. A counter drives i_tx_mii_am port with alignment marker insertion requests at the correct intervals.
  5. The client logic receives the same series of packets through RX MII interface.
  6. The client logic then checks the number of packets received.
The following sample output illustrates a successful simulation test run for a 100 Gbps, PCS Only IP core variation. Times are in picoseconds. 
waiting for o_tx_lanes_stable...
o_tx_lanes_stable is 1 at time                525000
waiting for tx_dll_lock....
TX DLL LOCK is 1 at time              19792913
waiting for tx_transfer_ready....
TX transfer ready is 1 at time              20112785
waiting for rx_transfer_ready....
RX transfer ready is 1 at time              31188353
EHIP PLD Ready out is 1 at time              31248000
EHIP reset out is 0 at time              31288000
EHIP reset ack is 0 at time              31663163
EHIP TX reset out is 0 at time              31776000
EHIP TX reset ack is 0 at time              81509883
waiting for EHIP Ready....
EHIP READY is 1 at time              81603179
EHIP RX reset out is 0 at time              81720000
waiting for rx reset ack....
EHIP RX reset ack is 0 at time              81789771
Waiting for RX Block Lock
EHIP Rx Block Lock  is high at time              87690743
Waiting for AM lock
EHIP Rx am Lock  is high at time              89748253
Waiting for RX alignment
RX deskew locked
RX lane alignment locked
Sending Packets
Receiving Packets
Address 0x0000f002 data 0x00000053
Total traffic cycle errors: 0
100G Traffic Test PASSED..!!!
**
** Testbench complete.
**
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