2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
Word Offset | Register Type |
---|---|
0x000000 | KR4 registers |
0x000300 | RX PHY registers |
0x000400 | TX MAC registers |
0x000500 | RX MAC registers |
0x000800 | TX Statistics Counter registers |
0x000900 | RX Statistics Counter registers |
0x001000 | Packet Client registers |
Addr |
Name |
Bit |
Description |
HW Reset Value |
Access |
---|---|---|---|---|---|
0x1000 | PKT_CL_SCRATCH | [31:0] | Scratch register available for testing. | RW | |
0x1001 | PKT_CL_CLNT | [31:0] | Four characters of IP block identification string "CLNT" | RO | |
0x1008 | Packet Size Configure | [29:0] | Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
|
0x25800040 | RW |
0x1009 | Packet Number Control | [31:0] | Specify the number of packets to transmit from the packet generator. | 0xA | RW |
0x1010 | PKT_GEN_TX_CTRL | [7:0] |
|
0x6 | RW |
0x1011 | Destination address lower 32 bits | [31:0] | Destination address (lower 32 bits) | 0x56780ADD | RW |
0x1012 | Destination address upper 16 bits | [15:0] | Destination address (upper 16 bits) | 0x1234 | RW |
0x1013 | Source address lower 32 bits | [31:0] | Source address (lower 32 bits) | 0x43210ADD | RW |
0x1014 | Source address upper 16 bits | [15:0] | Source address (upper 16 bits) | 0x8765 | RW |
0x1016 | PKT_CL_LOOPBACK_RESET | [0] | MAC loopback reset. Set to the value of 1 to reset the design example MAC loopback. | 1'b0 | RW |