1. Quick Start Guide
Updated for: |
---|
Intel® Quartus® Prime Design Suite 20.3 |
IP Version 19.3.0 |
The H-Tile Hard IP for Ethernet Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
In addition, you can download the compiled hardware design to the Intel® Stratix® 10 MX FPGA Development Kit. Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
- 100 Gbps MAC+PCS (supports simulation testbench, compilation-only example project, and hardware design example)
- 100 Gbps PCS only (supports simulation testbench and compilation-only example project, and hardware design example)
- 100 Gbps OTN (supports simulation testbench and compilation-only example project)
- 100 Gbps FlexE (supports simulation testbench and compilation-only example project)
Did you find the information on this page useful?
Characters remaining: