H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683314
Date 1/27/2021
Public
Download
Document Table of Contents

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.3
IP Version 19.3.0

The H-Tile Hard IP for Ethernet Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel® Stratix® 10 MX FPGA Development Kit. Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

You can generate the design example H-Tile Hard IP for Ethernet Intel FPGA IP core variation:
  • 100 Gbps MAC+PCS (supports simulation testbench, compilation-only example project, and hardware design example)
  • 100 Gbps PCS only (supports simulation testbench and compilation-only example project, and hardware design example)
  • 100 Gbps OTN (supports simulation testbench and compilation-only example project)
  • 100 Gbps FlexE (supports simulation testbench and compilation-only example project)
Note: The H-Tile Hard IP for Ethernet Intel FPGA IP provides preliminary support for the OTN feature. For further inquiries, contact your nearest Intel sales representative or file an Intel Premier Support (IPS) case on https://www.intel.com/content/www/us/en/programmable/my-intel/mal-home.html.
Figure 1. Development Steps for the Design ExampleFuture releases of the IP core also provide a hardware design example you can compile and test in hardware. The compilation-only example project cannot be configured in hardware.