H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.5. Hardware Design Example Components

The H-Tile Hard IP for Ethernet Intel FPGA hardware design example supports only the MAC + PCS and PCS Only variants.

Figure 10.  Intel® Stratix® 10 MX Development Kit Hardware Design Example High Level Block Diagram
The H-Tile Hard IP for Ethernet Intel FPGA hardware design example includes the following components:
  • H-Tile Hard IP for Ethernet Intel FPGA IP core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • One ATX PLL to generate the high speed serial clock to drive the device transceiver channels.
  • An I/O PLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.

The hardware design example uses run_test command to initiate packet transmission from packet generator to the IP core. The IP core receives the packets and transmit to the packet generator through the serial loopback. The client logic reads and print out the MAC statistic registers when the packet transmissions are complete.

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