Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

ID 683310
Date 12/18/2019
Document Table of Contents

10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments

Use the i++ command-line arguments to affect how your component is compiled and linked.

General i++ Command Options

Option Description
--debug-log Generate the compiler diagnostics log.
-h, --help List compiler command options along with brief descriptions.
-o result Place compiler output into the <result> executable and the <result>.prj directory.
-v Display messages describing the progress of the compilation.
--version Display compiler version information.

Command Options Affecting Compiling

Option Default Value Description
-c Preprocess, parse, and generate object files.
--component component name Comma-separated list of function names to synthesize to RTL.
To use this option, your component must be configured with C-linkage using the extern "C" specification. For example:
extern "C" int myComponent(int a, int b)

Using the component function attribute is preferred over using the --component command option to indicate functions that you want the compiler to synthesize.

-D macro [= val ] Define a <macro> with <val> as its value.
-g   Generate debug information (default option).
-g0   Do not generate debug information.
-I dir Add directory <dir> to the end of the main include path.
-march=[x86-64 | FPGA_family | FPGA_part_number] x86-64 Generate code for an emulator flow (x86-64) or for the specified FPGA family or FPGA part number.
--promote-integers Use extra FPGA resources to mimic g++ integer promotion.

In Pro Edition, the compiler always promotes integers for standard types. Use the ac_int datatypes if you want smaller (or larger) datatypes.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/integer_promotion

--quartus-compile Run the HDL generated through Intel® Quartus® Prime to generate accurate fMAX and area estimates. Your component is not expected to cleanly close timing.
--simulator simulator_name modelsim Specifies the simulator you are using to perform verification.
This command option can take the following values for <simulator_name>:
Use ModelSim* for component verification.
Disable verification. That is, generate RTL for components without the test bench.

If you do not specify this option, --simulator modelsim is assumed.

--fpc Remove intermediate rounding and conversion when possible.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--fp-relaxed Relax the order of floating point arithmetic operations.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--clock clock target 240 MHz Optimize the RTL for the specified clock frequency or period.
For example:
i++ -march="Arria 10" test.cpp --clock 100MHz
i++ -march="Arria 10" test.cpp --clock 10ns

Command Options Affecting Linking

Option Default Value Description
-ghdl Enable full debug visibility and logging of all HDL signals in simulation.
-L dir (Linux only) Add directory <dir> to the list of directories to be searched for library files specified with the -l option.
-l library (Linux only) Use the library name <library> when linking.
--x86-only   Create only the testbench executable ( <result>.out/ <result>.exe).
--fpga-only   Create only the <result>.prj directory and its contents.