Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

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ID 683310
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Standard Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary A. Supported Math Functions B. Intel® HLS Compiler Standard Edition Reference Manual Archives C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler x
2.1. Intel® HLS Compiler Standard Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Pipeline Approach
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Avalon® Memory-Mapped Master Interfaces 4.4. Slave Interfaces 4.5. Component Invocation Interface Arguments 4.6. Unstable and Stable Component Arguments 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Avalon® Memory-Mapped Master Interfaces x
4.3.1. Memory-Mapped Master Testbench Constructor 4.3.2. Implicit and Explicit Examples of Describing a Memory Interface
4.4. Slave Interfaces x
4.4.1. Control and Status Register (CSR) Slave 4.4.2. Slave Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Concurrency (max_concurrency Pragma) 6.5. Loop Unrolling (unroll Pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Integer Promotion and ac_int Data Types 8.3. Debugging Your Use of the ac_int Data Type 8.4. Declaring ac_fixed Data Types 8.5. AC Data Types and Native Compilers
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary x
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments 10.2. Intel® HLS Compiler Standard Edition Header Files 10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros 10.4. Intel® HLS Compiler Standard Edition Keywords 10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only) 10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes 10.7. Intel® HLS Compiler Standard Edition Loop Pragmas 10.8. Intel® HLS Compiler Standard Edition Component Attributes 10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces 10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments 10.11. Intel® HLS Compiler Standard Edition Component Macros 10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces 10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces 10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces 10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
A. Supported Math Functions x
A.1. Math Functions Provided by the math.h Header File A.2. Math Functions Provided by the extendedmath.h Header File A.3. Math Functions Provided by the ac_fixed_math.h Header File
1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual

10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments

Use the i++ command-line arguments to affect how your component is compiled and linked.

General i++ Command Options

Option Description
--debug-log Generate the compiler diagnostics log.
-h, --help List compiler command options along with brief descriptions.
-o result Place compiler output into the <result> executable and the <result>.prj directory.
-v Display messages describing the progress of the compilation.
--version Display compiler version information.

Command Options Affecting Compiling

Option Default Value Description
-c Preprocess, parse, and generate object files.
--component component name Comma-separated list of function names to synthesize to RTL.
To use this option, your component must be configured with C-linkage using the extern "C" specification. For example: 
extern "C" int myComponent(int a, int b)

Using the component function attribute is preferred over using the --component command option to indicate functions that you want the compiler to synthesize.

-D macro [= val ] Define a <macro> with <val> as its value.
-g   Generate debug information (default option).
-g0   Do not generate debug information.
-I dir Add directory <dir> to the end of the main include path.
-march=[x86-64 | FPGA_family | FPGA_part_number] x86-64 Generate code for an emulator flow (x86-64) or for the specified FPGA family or FPGA part number.
--promote-integers Use extra FPGA resources to mimic g++ integer promotion.

In Pro Edition, the compiler always promotes integers for standard types. Use the ac_int datatypes if you want smaller (or larger) datatypes.

To learn more, review the tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/integer_promotion

--quartus-compile Run the HDL generated through Intel® Quartus® Prime to generate accurate fMAX and area estimates. Your component is not expected to cleanly close timing.
--simulator simulator_name modelsim Specifies the simulator you are using to perform verification.
This command option can take the following values for <simulator_name>:
modelsim
Use ModelSim* for component verification.
none
Disable verification. That is, generate RTL for components without the test bench.

If you do not specify this option, --simulator modelsim is assumed.

--fpc Remove intermediate rounding and conversion when possible.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--fp-relaxed Relax the order of floating point arithmetic operations.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--clock clock target 240 MHz Optimize the RTL for the specified clock frequency or period.
For example: 
i++ -march="Arria 10" test.cpp --clock 100MHz
i++ -march="Arria 10" test.cpp --clock 10ns

Command Options Affecting Linking

Option Default Value Description
-ghdl Enable full debug visibility and logging of all HDL signals in simulation.
-L dir (Linux only) Add directory <dir> to the list of directories to be searched for library files specified with the -l option.
-l library (Linux only) Use the library name <library> when linking.
--x86-only   Create only the testbench executable ( <result>.out/ <result>.exe).
--fpga-only   Create only the <result>.prj directory and its contents.
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