Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

ID 683310
Date 12/18/2019
Document Table of Contents

2.1. Intel® HLS Compiler Standard Edition Command Options

Use the Intel® HLS Compiler Standard Edition command options to customize how the compiler performs general functions, customize file linking, or customize compilation.
Table 2.  General Command OptionsThese i++ command options perform general compiler functions.
Command Option Description
--debug-log Instructs the compiler to generate a log file that contains diagnostic information.

By default, the debug.log file is in the a.prj subdirectory within your current working directory.

If you also include the -o <result> command option, the debug.log file will be in the <result>.prj subdirectory.

If your compilation fails, the debug.log file is generated whether you set this option or not.

-h or --help Instructs the compiler to list all the command options and their descriptions on screen.
-o <result> Instructs the compiler to place its output into the <result> executable and the <result>.prj directory.

If you do not specify the -o <result>option, the compiler outputs an a.out file for Linux and an a.exe file for Windows. Use the -o <result> command option to specify the name of the compiler output.

Example command: i++ -o hlsoutput multiplier.c

Invoking this example command creates an hlsoutput executable for Linux and an hlsoutput.exe for Windows in your working directory.

-v Verbose mode that instructs the compiler to display messages describing the progress of the compilation.

Example command: i++ -v hls/multiplier/multiplier.c, where multiplier.c is the input file.

--version Instructs the compiler to display its version information on screen.

Command: i++ --version

Table 3.  Command Options that Customize CompilationThese i++ command options perform compiler functions that impact the translation from source file to object file.
Option Description
-c Instructs the compiler to preprocess, parse, and generate object files (.o/.obj) in the current working directory. The linking stage is omitted.

Example command: i++ -march="Arria 10" -c multiplier.c

Invoking this example command creates a multiplier.o file and sets the name of the <result>.prj directory to multiplier.prj.

When you later link the .o file, the -o option affects only the name of the executable file. The name of the <result>.prj directory remains unchanged from when the directory name was set by i++ -c command invocation.

--component <components> Allows you to specify a comma-separated list of function names that you want to the compiler to synthesize to RTL.

Example command: i++ counter.cpp --component count

To use this option, your component must be configured with C-linkage using the extern "C" specification. For example:
extern "C" int myComponent(int a, int b)

Using the component function attribute is preferred over using the --component command option to indicate functions that you want the compiler to synthesize.

-D <macro> [= <val> ] Allows you to pass a macro definition (<macro>) and its value (<val>) to the compiler.

If you do not a specify a value for <val>, its default value will be 1.

-g Generate debug information (default).
-g0 Do not generate debug information.
-I <dir> Adds a directory (<dir>) to the end of the include path list.
-march= [x86-64 | <FPGA_family> | <FPGA_part_number> Instructs the compiler to compile the component to the specified architecture or FPGA family.
The -march compiler option can take one of the following values:
Instructs the compiler to compile the code for an emulator flow.
Instructs the compiler to compile the code for a target FPGA device family.
The <FPGA_family> value can be any of the following device families:
  • ArriaV or "Arria V"
  • Arria10 or "Arria 10"
  • CycloneV or "Cyclone V"
  • MAX10 or "MAX 10" 1
  • StratixV or "Stratix V"
Quotation marks are required only if you specify a FPGA family name specifier that contains spaces
Instructs the compiler to compile the code for a target device. The compiler determines the FPGA device family from the FPGA part number that you specify here.

If you do not specify this option, -march=x86-64 is assumed.

If the parameter value that you specify contains spaces, surround the parameter value in quotation marks.

--promote-integers Instructs the compiler to use additional FPGA resources to mimic g++ integer promotion. Integer promotion occurs when all integer operations are carried out in 32 bits even if the largest operand is smaller than 32 bits.

The default behavior is to carry out integer operations in the size of the largest operand.

Refer to the <path to i++ installation>/examples/tutorials/best_practices/integer_promotion design example for usage information on the --promote-integers command option.

In Pro Edition, the compiler always promotes integers for standard types. Use the ac_int datatypes if you want smaller (or larger) datatypes.

--quartus-compile Compiles your HDL file with the Intel® Quartus® Prime compiler.

Example command: i++ --quartus-compile <input_files> ‑march="Arria 10"

When you specify this option, the Intel® Quartus® Prime compiler is run after the HDL is generated. The compiled Intel® Quartus® Prime project is put in the <result>.prj/quartus directory and a summary of the FPGA resource consumption and maximum clock frequency is added to the high level design reports in the <result>.prj/reports directory.

This compilation is intended to estimate the best achievable fMAX for your component. Your component is not expected to cleanly close timing in the reports.

--simulator <simulator_name> Specifies the simulator you are using to perform verification.
This command option can take the following values for <simulator_name>:
  • modelsim
  • none

If you do not specify this option, --simulator modelsim is assumed.

Important: The --simulator command option only works in conjunction with the -march command option.

The --simulator none option instructs the HLS compiler to skip the verification flow and generate RTL for the components without generating the corresponding test bench. If you use this option, the high-level design report (report.html) is generated more quickly but you cannot co-simulate your design. Without data from co-simulation, the report must omit verification statistics such as component latency.

Example command: i++ -march="<FPGA_family_or_part_number>" ‑‑simulator none multiplier.c

--fpc Remove intermediate rounding and conversion when possible.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--fp-relaxed Relax the order of floating point arithmetic operations.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--clock <clock_spec> Optimizes the RTL for the specified clock frequency or period.
Table 4.  Command Options that Customize File LinkingThese HLS command options specify compiler actions that impact the translation of the object file to the binary or RTL component.
Option Description
-ghdl Logs all signals when running the verification executable. After running the executable, the simulator logs waveforms to the a.prj/verification/vsim.wlf file.

For details about the ModelSim* waveform, see Debugging during Verification in Intel® High Level Synthesis Compiler Standard Edition User Guide.

-L <dir> (Linux only) Adds a directory (<dir>) to the end of the search path for the library files.
-l <library> (Linux only) Specifies the library file (.a) name when linking the object file to the binary.

On Windows, you can list library files (.lib) on the command line without specifying any command options or flags.

--x86-only Creates only the testbench executable.

The compiler outputs an <result> file for Linux or a <result>.exe file for Windows. The <result>.prj directory and its contents are not created.

--fpga-only Creates only the <result>.prj directory and its contents.

The testbench executable file ( <result> / <result>.exe) is not created.

Before you can co-simulate your hardware from a compilation output that uses this option, you must compile your testbench with the --x86-only option (or as part of a full compilation).

If you develop your component IP for Intel® MAX® 10 devices and you want to integrate your component IP into a system that you are developing in Intel® Quartus® Prime, ensure that the Intel® Quartus® Prime settings file (.qsf) for your system contains one of the following lines:
When you compile a component for the Intel® MAX® 10 device family with the Intel® HLS Compiler, the generated Intel® Quartus® Prime example project contains all of the required QSF settings for your component. However, the Intel® Quartus® Prime project for the system into which you integrate your component might not have the required QSF setting.