4.3.2. Implicit and Explicit Examples of Describing a Memory Interface

Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

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Date 12/18/2019

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4.3.2. Implicit and Explicit Examples of Describing a Memory Interface

Optimize component code that describes a memory interface by specifying an explicit mm_master object.

Implicit Example

The following code example arbitrates the load and store instructions from both pointer dereferences to a single interface on the component's top-level module. This interface will have a data bus width of 64 bits, an address width of 64 bits, and a fixed latency of 1.

#include "HLS/hls.h"
component void dut(int *ptr1, int *ptr2) {
 *ptr1 += *ptr2;
 *ptr2 += ptr1[1];
}

int main(void) {
  int x[2] = {0, 1};
  int y = 2;

  dut(x, &y);

  return 0;
}

Explicit Example

This example demonstrates how to optimize the previous code snippet for a specific memory interface using the explicit mm_master class. The mm_master class has a defined template, and it has the following characteristics:

Each interface is given a unique ID that infers two independent interfaces and reduces the amount of arbitration within the component.
The data bus width is larger than the default width of 64 bits.
The address bus width is smaller than the default width of 64 bits.
The interfaces have a fixed latency of 2.

By defining these characteristics, you state that your system returns valid read data after exactly two clock cycles and that the interface never stalls for both reads and writes, but the system must be able to provide two different memories. A unique physical Avalon® -MM master port ( as specified by the aspace parameter) is expected to correspond to a unique physical memory. If you connect multiple Avalon® -MM Master interfaces with different physical Avalon® -MM master ports to the same physical memory, the Intel® HLS Compiler cannot ensure functional correctness for any memory dependencies.

#include "HLS/hls.h"

typedef ihc::mm_master<int, ihc::dwidth<256>,
                            ihc::awidth<32>,
                            ihc::aspace<1>, 
                            ihc::latency<2> > Master1;
typedef ihc::mm_master<int, ihc::dwidth<256>,
                            ihc::awidth<32>,
                            ihc::aspace<4>,
                            ihc::latency<2> > Master2;

component void dut(Master1 &mm1,Master2 &mm2) {
  *mm1 += *mm2;
  *mm2 += mm1[1];
}
int main(void) {
  int x[2] = {0, 1};
  int y = 2;

  Master1 mm_x(x,2*sizeof(int),false);
  Master2 mm_y(&y,sizeof(int),false);

  dut(mm_x, mm_y);

  return 0;
}

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Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

4.3.2. Implicit and Explicit Examples of Describing a Memory Interface

Implicit Example

Explicit Example