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1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
4.1. Component Invocation Interface
4.2. Avalon® Streaming Interfaces
4.3. Avalon® Memory-Mapped Master Interfaces
4.4. Slave Interfaces
4.5. Component Invocation Interface Arguments
4.6. Unstable and Stable Component Arguments
4.7. Global Variables
4.8. Structs in Component Interfaces
4.9. Reset Behavior
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments
10.2. Intel® HLS Compiler Standard Edition Header Files
10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
10.4. Intel® HLS Compiler Standard Edition Keywords
10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only)
10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes
10.7. Intel® HLS Compiler Standard Edition Loop Pragmas
10.8. Intel® HLS Compiler Standard Edition Component Attributes
10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces
10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments
10.11. Intel® HLS Compiler Standard Edition Component Macros
10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces
10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces
10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces
10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
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4.4. Slave Interfaces
The Intel® HLS Compiler provides two different types of slave interfaces that you can use with a component.
In general, smaller scalar inputs should use slave registers. Large arrays should use slave memories if your intention is to copy these arrays into or out of the component.
Slave interfaces are implemented as Avalon® Memory Mapped ( Avalon® -MM) Slave interfaces. For details about the Avalon® -MM Slave interfaces, see "Avalon Memory-Mapped Interfaces in Avalon Interface Specifications.
| Slave Type | Associated Slave Interface | Read/Write Behavior | Synchronization | Read Latency | Controlling Interface Data Width |
|---|---|---|---|---|---|
| Register | The component control and status register (CSR) slave. | The component cannot update these registers from the datapath, so you can read back only data that you wrote in. | Synchronized with the component start signal. | Fixed value of 1. | Always 64 bits |
| Memory (M20K) | Dedicated slave interface on the component. | The component reads from this memory and updates it as it runs. Updates from the component datapath are visible in memory. |
Reads and writes to slave memories from outside of the component should occur only when your component is not executing. You might experience undefined component behavior if outside slave memory accesses occur when your component is executing. The undefined behavior can occur even if a slave memory access is to a memory address that the component does not access. |
Fixed value that is dependent on the component memory access pattern and any attributes or pragmas that you set. See the Component Viewer report in the High-Level Design Report (report.html) for the read latency of a specific slave memory argument. |
The data width is a multiple of the slave data type, where the multiple is determined by coalescing the internal accesses. |