Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

ID 683310
Date 12/18/2019
Document Table of Contents

4.4. Slave Interfaces

The Intel® HLS Compiler provides two different types of slave interfaces that you can use with a component.
In general, smaller scalar inputs should use slave registers. Large arrays should use slave memories if your intention is to copy these arrays into or out of the component.

Slave interfaces are implemented as Avalon® Memory Mapped ( Avalon® -MM) Slave interfaces. For details about the Avalon® -MM Slave interfaces, see "Avalon Memory-Mapped Interfaces in Avalon Interface Specifications.

Table 12.  Types of Slave Interfaces
Slave Type Associated Slave Interface Read/Write Behavior Synchronization Read Latency Controlling Interface Data Width
Register The component control and status register (CSR) slave. The component cannot update these registers from the datapath, so you can read back only data that you wrote in. Synchronized with the component start signal. Fixed value of 1. Always 64 bits
Memory (M20K) Dedicated slave interface on the component.

The component reads from this memory and updates it as it runs.

Updates from the component datapath are visible in memory.

Reads and writes to slave memories from outside of the component should occur only when your component is not executing.

You might experience undefined component behavior if outside slave memory accesses occur when your component is executing. The undefined behavior can occur even if a slave memory access is to a memory address that the component does not access.

Fixed value that is dependent on the component memory access pattern and any attributes or pragmas that you set.

See the Component Viewer report in the High-Level Design Report (report.html) for the read latency of a specific slave memory argument.

The data width is a multiple of the slave data type, where the multiple is determined by coalescing the internal accesses.