Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

ID 683310
Date 12/18/2019
Document Table of Contents

4.4.2. Slave Memories

By default, component functions access parameters that are passed by reference through an Avalon® Memory-Mapped (MM) Master interface. An alternative way to pass parameters by reference is to use an Avalon® MM Slave interface, which exists inside the component.
Having a pointer argument generate an Avalon® MM Master interface on the component has two potential disadvantages:
  • The master interface has a single port. If the component has multiple load-store sites, arbitration on that port might create stallable logic.
  • Depending on the system in which the component is instantiated, other masters might use the memory bus while the component is running and create undesirable stalls on the bus.

Because a slave memory is internal to the component, the HLS compiler can create a memory architecture that is optimized for the access pattern of the component such as creating banked memories or coalescing memories.

Slave memories differ from component memories because they can be accessed from an Avalon® MM Master outside of the component. Component memories are by definition restricted to the component and cannot be accessed outside the component.

Unlike component memory, you cannot explicitly configure slave memory arguments (for example, banking or coalescing). You must rely on the automatic configurations generated by the compiler. You can control the structure of your slave memories only by restructuring your load and store operations.

Important: Reads and writes to slave memories from outside of the component should occur only when your component is not executing. You might experience undefined component behavior if outside slave memory accesses occur when your component is executing. The undefined behavior can occur even if a slave memory access is to a memory address that the component does not access.

A component can have many slave memory interfaces. Unlike slave register arguments that are grouped together in the CSR slave interface, each slave memory has a separate interface with separate data buses. The slave memory interface data bus width is determined by the width of the slave type. If the internal accesses to the memory have been coalesced, the slave memory interface data bus width might be a multiple of the width of the slave type.

Argument Label Description
hls_avalon_slave_memory_argument Implement the argument, in on-chip memory blocks, which can be read from or written to over a dedicated slave interface.