AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

ID 683307
Date 12/15/2017
Public Plan the SerialLite III Interface

Follow these steps to plan the SerialLite III interface:
  1. In the Design Element list, select the SerialLite III sl3_0 design entity under IP_TOP_IO. The design example FPGA_TOP.vhd file specifies to only use the right side of the device.
    Figure 14. SerialLite III Locations Button
  2. Click the >> button next to the sl3_0 design element to display Legal Locations. Interface Planner shows 10 legal locations for the right side of the device.
    Figure 15. SerialLite III Legal Location
  3. Double-click the HSSI_DUPLUX_CHANNEL_CLUSTER_95 legal location to place the elements in the floorplan. This placement then assigns this SerialLite III IP to this fixed location.