1.4.1. Modifying the VHDL Generics
The FPGA_TOP.vhd file uses VHDL generics to pass parameters that scale the channels and activate which IP you require in the system. You can modify these generics to match your design requirements, as the following examples show.
FPGA_TOP has a simple clocking scheme that clocks all transceiver channels with the same transmit PLL. You can select whether the design example uses the CMU, ATX, or FPLL to clock the transceivers. Select the CMU, ATX, or FPLL within sixpack configuration. Select xN (ATX or FPLL) for outside sixpack configuration. Use of the CMU is not an option for outside sixpack configurations. You can also modify the design to implement a more complex clocking scheme. The REFCLK pins for the standard and enhanced pcs transceivers and their IP protocols are at fixed pin locations on the left and right-hand side of the device to make the pin planning easier.
Modifying PCS Channels of a Transceiver in FPGA_TOP.vhd
The following example shows activating the standard PCS transceiver channels by setting the Boolean expression to true, and setting the number of channels to 2:
ACTIVATE_TXCVR_STD_L : boolean:= true;
TXCVR_STD_NUM_CHANNELS_L : integer:= 2;Conversely, the following example deactivates the enhanced PCS transceiver channels by setting the Boolean expression to false and setting the number of channels to 1:
ACTIVATE_TXCVR_ENH_L : boolean:= false;
TXCVR_ENH_NUM_CHANNELS_L : integer:= 1;Modifying Transceiver PLL Type and Clock Line in FPGA_TOP.vhd
The following example shows changing the Transceiver PLL type and clock line by modifying the TX_PLL_TYPE strings in FPGA_TOP.vhd:
-- LEFT HAND SIDE TX PLL SELECTION
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_STD_L : string:= "ATX_xN";
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_ENH_L : string:= "ATX_xN";
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_IP_PCIE_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_TSE_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_XAUI_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_ONEG_TENG_BASE_KR_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_SLIII_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_LL_40G_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_ILKN_100G_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_JESD204B_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_SDI_TRIPLERATE_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_DISPLAYPORT_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_HDMI_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_MULTIRATE_ETH_L : string:= "ATX_xN";Complete Modification Example
The following example shows changes to FPGA_TOP.vhd to implement the following design requirement specifications:
FPGA Left Side Specifications
- 2 x transceiver channel using standard PCS
- 1 x PCIe* Gen 3 x 8
- ATX with PLL with xN line clocking
ACTIVATE_TXCVR_STD_L : boolean:= true;
TXCVR_STD_NUM_CHANNELS_L : integer:= 2;
ACTIVATE_PCIe_g3x8_L : boolean:= true;
PCIe_g3x8_NUM_INSTANCES_L : integer:= 1;
-- LEFT HAND SIDE TX PLL SELECTION
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_STD_L : string:= "ATX_xN";
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_ENH_L : string:= "ATX_xN";
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_IP_PCIE_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_TSE_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_XAUI_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_ONEG_TENG_BASE_KR_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_SLIII_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_LL_40G_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_ILKN_100G_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_JESD204B_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_SDI_TRIPLERATE_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_DISPLAYPORT_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_HDMI_L : string:= "ATX_xN";
TX_PLL_TYPE_IP_MULTIRATE_ETH_L : string:= "ATX_xN";FPGA Right Side Specifications
- 2 x transceiver channel using enhanced PCS
- 1 x SerialLite III IP
- ATX with PLL with xN line clocking
ACTIVATE_TXCVR_ENH_R : boolean:= true;
TXCVR_ENH_NUM_CHANNELS_R : integer:= 2;
ACTIVATE_SLIII_R : boolean:= true;
SLIII_NUM_CHANNELS_R : integer:= 1;
-- RIGHT HAND SIDE TX PLL SELECTION
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_STD_R : string := "ATX_xN";
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_ENH_R : string := "ATX_xN";
-- Enter "ATX, "ATX_xN", "CMU", "FPLL" or "FPLL_xN"
TX_PLL_TYPE_IP_PCIE_R : string := "ATX_xN";
TX_PLL_TYPE_IP_TSE_R : string := "ATX_xN";
TX_PLL_TYPE_IP_XAUI_R : string := "ATX_xN";
TX_PLL_TYPE_IP_ONEG_TENG_BASE_KR_R : string := "ATX_xN";
TX_PLL_TYPE_IP_SLIII_R : string := "ATX_xN";
TX_PLL_TYPE_IP_LL_40G_R : string := "ATX_xN";
TX_PLL_TYPE_IP_ILKN_100G_R : string := "ATX_xN";
TX_PLL_TYPE_IP_JESD204B_R : string := "ATX_xN";
TX_PLL_TYPE_IP_SDI_TRIPLERATE_R : string := "ATX_xN";
TX_PLL_TYPE_IP_DISPLAYPORT_R : string := "ATX_xN";
TX_PLL_TYPE_IP_HDMI_R : string := "ATX_xN";
TX_PLL_TYPE_IP_MULTIRATE_ETH_R : string := "ATX_xN";