1.1. FPGA_TOP Design Example Overview
FPGA_TOP is a transceiver and EMIF based design that comprises a hierarchy of six main VHDL blocks. By default, the design targets an Intel® Stratix® 10 1SG280HU1F50E1VG device. This device provides 96 transceivers, 4 x PCIe* Hard IP blocks, and 4 x 100G MAC that the design requires. The FPGA_TOP design example is ready to use with this application note, or you can optionally modify this the design example to suit your system requirements, as Modifying the FPGA_TOP Design Example describes.
FPGA_GX_BLK does not support every combination of a transceiver based design. More complex bonding schemes, such as schemes that require a mixture of TX PLLs, require more adaptations of this design example. Refer to the Intel® Stratix® 10 GX/SX Device Overview for the quantity and type of resources in Intel® Stratix® 10 devices.
The remainder of this document describes the design example blocks, and provides a walkthrough of pin planning with Interface Planner.
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