AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.1. FPGA_TOP Design Example Overview

This application note uses the FPGA_TOP Intel® Stratix® 10 design example to illustrate pin planning with Interface Planner.
FPGA_TOP Design Example Block Diagram

FPGA_TOP is a transceiver and EMIF based design that comprises a hierarchy of six main VHDL blocks. By default, the design targets an Intel® Stratix® 10 1SG280HU1F50E1VG device. This device provides 96 transceivers, 4 x PCIe* Hard IP blocks, and 4 x 100G MAC that the design requires. The FPGA_TOP design example is ready to use with this application note, or you can optionally modify this the design example to suit your system requirements, as Modifying the FPGA_TOP Design Example describes.

Figure 2. FPGA_GX_BLK Transceiver Based System


FPGA_GX_BLK does not support every combination of a transceiver based design. More complex bonding schemes, such as schemes that require a mixture of TX PLLs, require more adaptations of this design example. Refer to the Intel® Stratix® 10 GX/SX Device Overview for the quantity and type of resources in Intel® Stratix® 10 devices.

The remainder of this document describes the design example blocks, and provides a walkthrough of pin planning with Interface Planner.

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