AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

ID 683307
Date 12/15/2017
Public Plan the External Memory Interface

Follow these steps to plan the pinout of the EMIF interface by identifying legal and available placement locations.
  1. In the Interface Planner Plan tab, click the IP filter button. This filter automatically shows only the IP in the design example.
  2. In the Design Elements list, expand the EMIF_TOP_I0 block, and then select the emif_s10_0 design element.
  3. Click the >> button next to the emif_s10_0 design element name to display the Legal Locations for placement.
    Figure 9. Locations List Button
  4. Select any legal location in the list to highlight that floorplan location. For example, click EMIF_L12_X53_Y325_Y400 in the Locations list. The location you select highlights in the floorplan.
    Figure 10. Location Selected
  5. Double-click EMIF_L12_X53_Y325_Y400 in the Legal Locations list to place the entity at the location.
    Figure 11. EMIF Fixed Locations

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