AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

Download
ID 683307
Date 12/15/2017
Public

1. Interface Planning for Intel® Stratix® 10 FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 17.1
This application note demonstrates Intel® Stratix® 10 interface pin planning with the Intel® Quartus® Prime Pro Edition Interface Planner.

The Interface Planner is a graphical planning tool that allows you to visualize and rapidly define a legal device floorplan before creating the final pinout for PCB manufacture. This application note walks you through Interface Planner pin planning for a transceiver based design that also includes an external memory interface (EMIF).

Figure 1.  Intel® Quartus® Prime Pro Edition Interface Planner

Did you find the information on this page useful?

Characters remaining:

Feedback Message