AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

ID 683307
Date 12/15/2017
Public Plan the PCIe* Interface

The Interface Planner helps you to locate available locations and pin placement for the Intel® FPGA IP for PCIe* and the SerialLite III Intel® FPGA IP interfaces. The following sections describe planning for these IP.

Follow these steps to plan the PCIe* interface:

  1. In Interface Planner, click the IP filter button.
  2. In the Design Elements list, expand the IP_TOP_I0 block to select the PCIe* dut design element. The design example FPGA_TOP.vhd file specifies to only use the left side of the device.
  3. Click the >> button next to dut to display Legal Locations for placement. Interface Planner shows one legal location for the left side of the device.
    Figure 12. Legal Locations Button
  4. Double-click the HSSI_DUPLUX_CHANNEL_CLUSTER_24 to place the elements in the floorplan. This placement then assigns this PCIe* IP to this fixed location.
    Figure 13. PCIe Fixed Placement