AN 821: Interface Planning for Intel® Stratix® 10 FPGAs

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ID 683307
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. Interface Planning for Intel® Stratix® 10 FPGAs
1. Interface Planning for Intel® Stratix® 10 FPGAs x
1.1. FPGA_TOP Design Example Overview 1.2. Design Example Files 1.3. Design Example Walkthrough 1.4. Modifying the FPGA_TOP Design Example 1.5. Document Revision History
1.3. Design Example Walkthrough x
1.3.1. Step 1: Project Setup 1.3.2. Step 2: Initialize Interface Planner 1.3.3. Step 3: Update Plan with Project Assignments 1.3.4. Step 4: Plan Periphery Placement 1.3.5. Step 5: Report Placement Data 1.3.6. Step 6: Validate and Export Plan Constraints 1.3.7. Step 7: Apply Plan Constraints
1.3.4. Step 4: Plan Periphery Placement x
1.3.4.1. Plan the External Memory Interface 1.3.4.2. Plan the PCIe* Interface 1.3.4.3. Plan the SerialLite III Interface 1.3.4.4. Plan the Transceiver PHY Interface 1.3.4.5. Complete and Save the Floorplan
1.4. Modifying the FPGA_TOP Design Example x
1.4.1. Modifying the VHDL Generics 1.4.2. Changing the Target FPGA
1. Interface Planning for Intel® Stratix® 10 FPGAs

1.3.4.4. Plan the Transceiver PHY Interface

Follow these steps to identify legal locations and place FPGA_GX_BLK.
  1. In the Design Elements list, expand the TXCVR_TOP_I0 block to find the xcvr_native_s10_htile_0 transceiver PHY design element. The design example FPGA_TOP.vhd file specifies to use the left and right sides of the device.
  2. Click the >> button next to the xcvr_native_s10_htile_0 design element to display Legal Locations. Interface Planner shows more than 10 legal locations for the left and right sides of the device.
  3. To automatically place the elements in a legal location, right-click the xcvr_native_s10_htile_0 and click Autoplace Selected. This placement then assigns this GX_BLK to a fixed location on the left and right sides of the device.
    Figure 16. Transceiver Native PHY Fixed Placement
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