188.8.131.52. Plan the Transceiver PHY Interface
Follow these steps to identify legal locations and place FPGA_GX_BLK.
- In the Design Elements list, expand the TXCVR_TOP_I0 block to find the xcvr_native_s10_htile_0 transceiver PHY design element. The design example FPGA_TOP.vhd file specifies to use the left and right sides of the device.
- Click the >> button next to the xcvr_native_s10_htile_0 design element to display Legal Locations. Interface Planner shows more than 10 legal locations for the left and right sides of the device.
- To automatically place the elements in a legal location, right-click the xcvr_native_s10_htile_0 and click Autoplace Selected. This placement then assigns this GX_BLK to a fixed location on the left and right sides of the device.
Figure 16. Transceiver Native PHY Fixed Placement
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