Nios II Classic Software Developer’s Handbook

ID 683282
Date 5/14/2015
Public
Document Table of Contents

4.11.3.3.3. elf2dat

Description

Converts a .elf file to a .dat file format appropriate for Verilog HDL hardware simulators.

Usage

elf2dat --infile=file --outfile=file --width=width --base=address
               --end=address [--pad=number] [--create-lanes=number]
               [--little-endian-mem] [--big-endian-mem]

Options

   --infile=<elf-input-filename>
    --outfile=<dat-output-filename>
    --base=<base address>
    --end=<end address>
    --pad=[0 | 1] (default 1)
    --create-lanes=[0 | 1] (default 0)
    --width=[ 8 | 16 | 32 | 64 | 128]
    --little-endian-mem
    --big-endian-mem

Transforms the data within an ELF file in the address range [base, end] into the corresponding DAT file. Lane files are optionally created (--create-lanes=1, default is 0). Lane file names are generated based on the output file by inserting "_lane0", "_lane1", etc. before the ".dat" extension of the output filename. If "--pad=1" is specified, any unspecified locations in memory will be filled with zeros. If "--little-endian-mem" is specified, the memory is assumed to be little-endian. If "--big-endian-mem" is specified, the memory is assumed to be big-endian. If neither --little-endian-mem or --big-endian-mem is specified, the memory is assumed to be little-endian. Note that the endianness of the ELF file never effects the result.

Example

elf2dat --infile=foo.elf --outfile=bar.dat --width=32 --create-lanes=1
            --base=0 --end=0x1000

will create DAT files bar.dat, bar_lane0.dat, bar_lane1.dat, bar_lane2.dat, bar_lane3.dat