Nios II Classic Software Developer’s Handbook

ID 683282
Date 5/14/2015
Public
Document Table of Contents

8.6.1.1. Exception Cause Codes

Table 44.  Nios II Exception Cause Codes
Exception Cause Code Cause Symbol 8
Reset 0 NIOS2_EXCEPTION_RESET
Processor-only Reset Request 1 NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST
Hardware Interrupt 2 NIOS2_EXCEPTION_INTERRUPT
Trap Instruction 3 NIOS2_EXCEPTION_TRAP_INST
Unimplemented Instruction 4 NIOS2_EXCEPTION_UNIMPLEMENTED_INST
Illegal Instruction 5 NIOS2_EXCEPTION_ILLEGAL_INST
Misaligned Data Address 6 NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR
Misaligned Destination Address 7 NIOS2_EXCEPTION_MISALIGNED_TARGET_PC
Division Error 8 NIOS2_EXCEPTION_DIVISION_ERROR
Supervisor-only Instruction Address 9 NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR
Supervisor-only Instruction 10 NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST
Supervisor-only Data Address 11 NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR
Translation lookaside buffer (TLB) Miss 12 NIOS2_EXCEPTION_TLB_MISS
TLB Permission Violation (execute) 13 NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION
TLB Permission Violation (read) 14 NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION
TLB Permission Violation (write) 15 NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION
MPU Region Violation (instruction) 16 NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION
MPU Region Violation (data) 17 NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION
Cause unknown9 -1 NIOS2_EXCEPTION_CAUSE_NOT_PRESENT

If there is an instruction-related exception handler, it is called at the end of the software exception funnel (if the funnel has not recognized a hardware interrupt, unimplemented instruction or trap). It takes the place of the break or infinite loop. Therefore, to support debugging, execute a break on a trap instruction.

Note: It is possible for an instruction-related exception to occur during execution of an ISR.
8 Cause symbols are defined in sys/alt_exceptions.h.
9 This value is passed to the instruction-related exception handler if the cause argument if the cause is not known; for example, if the cause register not implemented in the Nios II processor core.